?? cnt10.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk:in std_logic;
c10:out std_logic);
end;
architecture one of cnt10 is
signal q: std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
if (q<9) then q<=q+1;
else q<="0000";
end if;
end if;
end process;
process(q)
begin
if q<5 then c10<='0';
else c10<='1';
end if;
end process;
end;
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