library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ADDER6B is
  port(A6B:in std_logic_vector(5 downto 0);
       B6B:in std_logic_vector(5 downto 0);
       S6B:out std_logic_vector(5 downto 0));
end;
architecture ONE of ADDER6B is
begin
S6B<=A6B+B6B;
end;