?? at91rm9200_inc.h
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#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Two-wire Interface
// *****************************************************************************
// *** Register offset in AT91S_TWI structure ***
#define TWI_CR ( 0) // Control Register
#define TWI_MMR ( 4) // Master Mode Register
#define TWI_SMR ( 8) // Slave Mode Register
#define TWI_IADR (12) // Internal Address Register
#define TWI_CWGR (16) // Clock Waveform Generator Register
#define TWI_SR (32) // Status Register
#define TWI_IER (36) // Interrupt Enable Register
#define TWI_IDR (40) // Interrupt Disable Register
#define TWI_IMR (44) // Interrupt Mask Register
#define TWI_RHR (48) // Receive Holding Register
#define TWI_THR (52) // Transmit Holding Register
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled
#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled
#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read
#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access
#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access
#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Multimedia Card Interface
// *****************************************************************************
// *** Register offset in AT91S_MCI structure ***
#define MCI_CR ( 0) // MCI Control Register
#define MCI_MR ( 4) // MCI Mode Register
#define MCI_DTOR ( 8) // MCI Data Timeout Register
#define MCI_SDCR (12) // MCI SD Card Register
#define MCI_ARGR (16) // MCI Argument Register
#define MCI_CMDR (20) // MCI Command Register
#define MCI_RSPR (32) // MCI Response Register
#define MCI_RDR (48) // MCI Receive Data Register
#define MCI_TDR (52) // MCI Transmit Data Register
#define MCI_SR (64) // MCI Status Register
#define MCI_IER (68) // MCI Interrupt Enable Register
#define MCI_IDR (72) // MCI Interrupt Disable Register
#define MCI_IMR (76) // MCI Interrupt Mask Register
#define MCI_RPR (256) // Receive Pointer Register
#define MCI_RCR (260) // Receive Counter Register
#define MCI_TPR (264) // Transmit Pointer Register
#define MCI_TCR (268) // Transmit Counter Register
#define MCI_RNPR (272) // Receive Next Pointer Register
#define MCI_RNCR (276) // Receive Next Counter Register
#define MCI_TNPR (280) // Transmit Next Pointer Register
#define MCI_TNCR (284) // Transmit Next Counter Register
#define MCI_PTCR (288) // PDC Transfer Control Register
#define MCI_PTSR (292) // PDC Transfer Status Register
// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable
#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable
#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable
#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable
// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
#define AT91C_MCI_CLKDIV (0x1 << 0) // (MCI) Clock Divider
#define AT91C_MCI_PWSDIV (0x1 << 8) // (MCI) Power Saving Divider
#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value
#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode
#define AT91C_MCI_BLKLEN (0x1 << 18) // (MCI) Data Block Length
// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
#define AT91C_MCI_DTOCYC (0x1 << 0) // (MCI) Data Timeout Cycle Number
#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier
#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1
#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16
#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128
#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256
#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024
#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096
#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536
#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576
// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
#define AT91C_MCI_SCDSEL (0x1 << 0) // (MCI) SD Card Selector
#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SD Card Bus Width
// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
#define AT91C_MCI_CMDNB (0x1F << 0) // (MCI) Command Number
#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type
#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response
#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response
#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response
#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD
#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD
#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD
#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD
#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command
#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response
#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command
#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond
#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD
#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer
#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer
#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer
#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction
#define AT91C_MCI_TRTYP (0x3 << 19) // (MCI) Transfer Type
#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) Block Transfer type
#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) Multiple Block transfer type
#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) Stream transfer type
// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag
#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag
#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag
#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag
#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag
#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag
#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag
#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag
#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag
#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag
#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag
#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag
#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag
#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag
#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag
#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag
#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag
#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag
#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag
// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- ?? 快捷鍵說明
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