<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_COMP"></a><b>EMAC_COMP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_COMP">AT91C_EMAC_COMP</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_UND"></a><b>EMAC_UND</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_UND">AT91C_EMAC_UND</a></font></td><td><b></b><br>Transmit underrun. Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC. Cleared by writing a one to this bit.</td></tr>
</null></table>
<a name="EMAC_RBQP"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_RBQP  <i>Receive Buffer Queue Pointer</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_RBQP">AT91C_EMAC_RBQP</a></i> 0xFFFBC018</font></null></ul><br>Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. The receive buffer is forced to word alignment.<a name="EMAC_RSR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_RSR  <i>Receive Status Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_RSR">AT91C_EMAC_RSR</a></i> 0xFFFBC020</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_BNA"></a><b>EMAC_BNA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_BNA">AT91C_EMAC_BNA</a></font></td><td><b></b><br>Buffer not available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_REC"></a><b>EMAC_REC</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_REC">AT91C_EMAC_REC</a></font></td><td><b></b><br>Frame received. One or more frames have been received and placed in memory. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_OVR"></a><b>EMAC_OVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_OVR">AT91C_EMAC_OVR</a></font></td><td><b></b><br>Ethernet transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when bit BNQ was not set. Cleared by writing a one to this bit.</td></tr>
</null></table>
<a name="EMAC_ISR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_ISR  <i>Interrupt Status Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_ISR">AT91C_EMAC_ISR</a></i> 0xFFFBC024</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_DONE"></a><b>EMAC_DONE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_DONE">AT91C_EMAC_DONE</a></font></td><td><b></b><br>Management done. The PHY maintenance register has completed its operation. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_RCOM"></a><b>EMAC_RCOM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RCOM">AT91C_EMAC_RCOM</a></font></td><td><b></b><br>Receive complete. A frame has been stored in memory. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RBNA"></a><b>EMAC_RBNA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RBNA">AT91C_EMAC_RBNA</a></font></td><td><b></b><br>Receive buffer not available. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TOVR"></a><b>EMAC_TOVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TOVR">AT91C_EMAC_TOVR</a></font></td><td><b></b><br>Transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_TUND"></a><b>EMAC_TUND</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TUND">AT91C_EMAC_TUND</a></font></td><td><b></b><br>Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_RTRY"></a><b>EMAC_RTRY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RTRY">AT91C_EMAC_RTRY</a></font></td><td><b></b><br>Transmit error. Retry limit exceeded. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_TBRE"></a><b>EMAC_TBRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TBRE">AT91C_EMAC_TBRE</a></font></td><td><b></b><br>Transmit buffer register empty. Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_TCOM"></a><b>EMAC_TCOM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TCOM">AT91C_EMAC_TCOM</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="EMAC_TIDLE"></a><b>EMAC_TIDLE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TIDLE">AT91C_EMAC_TIDLE</a></font></td><td><b></b><br>Transmit idle. Set when all frames have been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_LINK"></a><b>EMAC_LINK</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_LINK">AT91C_EMAC_LINK</a></font></td><td><b></b><br>Set when LINK pin changes value. Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="EMAC_ROVR"></a><b>EMAC_ROVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_ROVR">AT91C_EMAC_ROVR</a></font></td><td><b></b><br>RX overrun. Set when the RX overrun status bit is set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="EMAC_HRESP"></a><b>EMAC_HRESP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_HRESP">AT91C_EMAC_HRESP</a></font></td><td><b></b><br>HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.</td></tr>
</null></table>
<a name="EMAC_IER"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_IER">AT91C_EMAC_IER</a></i> 0xFFFBC028</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_DONE"></a><b>EMAC_DONE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_DONE">AT91C_EMAC_DONE</a></font></td><td><b></b><br>Management done. The PHY maintenance register has completed its operation. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_RCOM"></a><b>EMAC_RCOM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RCOM">AT91C_EMAC_RCOM</a></font></td><td><b></b><br>Receive complete. A frame has been stored in memory. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RBNA"></a><b>EMAC_RBNA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RBNA">AT91C_EMAC_RBNA</a></font></td><td><b></b><br>Receive buffer not available. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TOVR"></a><b>EMAC_TOVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TOVR">AT91C_EMAC_TOVR</a></font></td><td><b></b><br>Transmit buffer overrun. Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_TUND"></a><b>EMAC_TUND</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TUND">AT91C_EMAC_TUND</a></font></td><td><b></b><br>Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_RTRY"></a><b>EMAC_RTRY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_RTRY">AT91C_EMAC_RTRY</a></font></td><td><b></b><br>Transmit error. Retry limit exceeded. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_TBRE"></a><b>EMAC_TBRE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TBRE">AT91C_EMAC_TBRE</a></font></td><td><b></b><br>Transmit buffer register empty. Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_TCOM"></a><b>EMAC_TCOM</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TCOM">AT91C_EMAC_TCOM</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="EMAC_TIDLE"></a><b>EMAC_TIDLE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_TIDLE">AT91C_EMAC_TIDLE</a></font></td><td><b></b><br>Transmit idle. Set when all frames have been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_LINK"></a><b>EMAC_LINK</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_LINK">AT91C_EMAC_LINK</a></font></td><td><b></b><br>Set when LINK pin changes value. Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="EMAC_ROVR"></a><b>EMAC_ROVR</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_ROVR">AT91C_EMAC_ROVR</a></font></td><td><b></b><br>RX overrun. Set when the RX overrun status bit is set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="EMAC_HRESP"></a><b>EMAC_HRESP</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_HRESP">AT91C_EMAC_HRESP</a></font></td><td><b></b><br>HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.</td></tr>
</null></table>
<a name="EMAC_IDR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> EMAC_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>EMAC</b> <i><a href="AT91RM9200_h.html#AT91C_EMAC_IDR">AT91C_EMAC_IDR</a></i> 0xFFFBC02C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_DONE"></a><b>EMAC_DONE</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_EMAC_DONE">AT91C_EMAC_DONE</a></font></td><td><b></b><br>Management done. The PHY maintenance register has completed its operation. Cleared on read.</td></tr>