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<h1>Clock Generator Controler Peripheral</h1>
<null><a name="CKGR"></a><b>CKGR</b> <i><font size="-1">(<a href="AT91RM9200_h.html#AT91S_CKGR">AT91S_CKGR</a>)</font></i><b> 0xFFFFFC20 </b><i><font size="-1">(<a href="AT91RM9200_h.html#AT91C_BASE_CKGR">AT91C_BASE_CKGR</a>)</font></i>
<br></null><a name="CKGR"></a><h2>CKGR Software API <i><font size="-1">(<a href="AT91RM9200_h.html#AT91S_CKGR">AT91S_CKGR</a>)</font></i></h2>
<a name="CKGR"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91RM9200_CKGR.html#CKGR_MOR">CKGR_MOR</a></font></td><td><font size="-1">Main Oscillator Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91RM9200_CKGR.html#CKGR_MCFR">CKGR_MCFR</a></font></td><td><font size="-1">Main Clock Frequency Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x8</b></font></td><td><font size="-1"><a href="AT91RM9200_CKGR.html#CKGR_PLLAR">CKGR_PLLAR</a></font></td><td><font size="-1">PLL A Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91RM9200_CKGR.html#CKGR_PLLBR">CKGR_PLLBR</a></font></td><td><font size="-1">PLL B Register</font></td></tr>
</null></table><br></null><h2>CKGR Register Description</h2>
<null><a name="CKGR_MOR"></a><h4><a href="#CKGR">CKGR</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> CKGR_MOR <i>Main Oscillator Register</i></h4><ul><null><font size="-2"><li><b>CKGR</b> <i><a href="AT91RM9200_h.html#AT91C_CKGR_MOR">AT91C_CKGR_MOR</a></i> 0xFFFFFC20</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="CKGR_MOSCEN"></a><b>CKGR_MOSCEN</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_MOSCEN">AT91C_CKGR_MOSCEN</a></font></td><td><b>Main Oscillator Enable</b><br>0 = The main oscillator is disabled.<br>1 = The main oscillator is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="CKGR_OSCTEST"></a><b>CKGR_OSCTEST</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OSCTEST">AT91C_CKGR_OSCTEST</a></font></td><td><b>Oscillator Test</b><br>Please contact Atmel IP Support for further information.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..8</td><td align="CENTER"><a name="CKGR_OSCOUNT"></a><b>CKGR_OSCOUNT</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OSCOUNT">AT91C_CKGR_OSCOUNT</a></font></td><td><b>Main Oscillator Start-up Time</b><br>Specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time.</td></tr>
</null></table>
<a name="CKGR_MCFR"></a><h4><a href="#CKGR">CKGR</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> CKGR_MCFR <i>Main Clock Frequency Register</i></h4><ul><null><font size="-2"><li><b>CKGR</b> <i><a href="AT91RM9200_h.html#AT91C_CKGR_MCFR">AT91C_CKGR_MCFR</a></i> 0xFFFFFC24</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="CKGR_MAINF"></a><b>CKGR_MAINF</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_MAINF">AT91C_CKGR_MAINF</a></font></td><td><b>Main Clock Frequency</b><br>Gives the number of main clock cycles within 16 slow clock periods.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="CKGR_MAINRDY"></a><b>CKGR_MAINRDY</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_MAINRDY">AT91C_CKGR_MAINRDY</a></font></td><td><b>Main Clock Ready</b><br>0 = FMAIN value is not valid or the main oscillator is disabled.<br>1 = The main oscillator has been enabled previously and MAINF value is available.</td></tr>
</null></table>
<a name="CKGR_PLLAR"></a><h4><a href="#CKGR">CKGR</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> CKGR_PLLAR <i>PLL A Register</i></h4><ul><null><font size="-2"><li><b>CKGR</b> <i><a href="AT91RM9200_h.html#AT91C_CKGR_PLLAR">AT91C_CKGR_PLLAR</a></i> 0xFFFFFC28</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="CKGR_DIVA"></a><b>CKGR_DIVA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_DIVA">AT91C_CKGR_DIVA</a></font></td><td><b>Divider Selected</b><br>2-255 Divider output is the selected clock divided by DIVA<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_DIVA_0"></a><b>CKGR_DIVA_0</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_DIVA_0">AT91C_CKGR_DIVA_0</a></font></td><td><br>Divider output is 0</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_DIVA_BYPASS"></a><b>CKGR_DIVA_BYPASS</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_DIVA_BYPASS">AT91C_CKGR_DIVA_BYPASS</a></font></td><td><br>Divider is bypassed</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13..8</td><td align="CENTER"><a name="CKGR_PLLACOUNT"></a><b>CKGR_PLLACOUNT</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_PLLACOUNT">AT91C_CKGR_PLLACOUNT</a></font></td><td><b>PLL A Counter</b><br>Specifies the number of slow clock cycles before the LOCKA bit is set in APMC_SR after APMC_PLLA is written.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="CKGR_OUTA"></a><b>CKGR_OUTA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTA">AT91C_CKGR_OUTA</a></font></td><td><b>PLL A Output Frequency Range</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_OUTA_0"></a><b>CKGR_OUTA_0</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTA_0">AT91C_CKGR_OUTA_0</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_OUTA_1"></a><b>CKGR_OUTA_1</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTA_1">AT91C_CKGR_OUTA_1</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="CKGR_OUTA_2"></a><b>CKGR_OUTA_2</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTA_2">AT91C_CKGR_OUTA_2</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="CKGR_OUTA_3"></a><b>CKGR_OUTA_3</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTA_3">AT91C_CKGR_OUTA_3</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">26..16</td><td align="CENTER"><a name="CKGR_MULA"></a><b>CKGR_MULA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_MULA">AT91C_CKGR_MULA</a></font></td><td><b>PLL A Multiplier</b><br>0 = The PLL A is deactivated.<br>1 up to 2047 = The PLL A output frequency is the PLL A input frequency multiplied by MULA + 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">29</td><td align="CENTER"><a name="CKGR_SRCA"></a><b>CKGR_SRCA</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_SRCA">AT91C_CKGR_SRCA</a></font></td><td><b>PLL A Source</b><br>0 = The Divider A source is the slow clock.<br>1 = The Divider A source is the main clock.</td></tr>
</null></table>
<a name="CKGR_PLLBR"></a><h4><a href="#CKGR">CKGR</a>: <i><a href="AT91RM9200_h.html#AT91_REG">AT91_REG</a></i> CKGR_PLLBR <i>PLL B Register</i></h4><ul><null><font size="-2"><li><b>CKGR</b> <i><a href="AT91RM9200_h.html#AT91C_CKGR_PLLBR">AT91C_CKGR_PLLBR</a></i> 0xFFFFFC2C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="CKGR_DIVB"></a><b>CKGR_DIVB</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_DIVB">AT91C_CKGR_DIVB</a></font></td><td><b>Divider Selected</b><br>2-255 Divider output is the selected clock divided by DIVB<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_DIVB_0"></a><b>CKGR_DIVB_0</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_DIVB_0">AT91C_CKGR_DIVB_0</a></font></td><td><br>Divider output is 0</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_DIVB_BYPASS"></a><b>CKGR_DIVB_BYPASS</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_DIVB_BYPASS">AT91C_CKGR_DIVB_BYPASS</a></font></td><td><br>Divider is bypassed</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13..8</td><td align="CENTER"><a name="CKGR_PLLBCOUNT"></a><b>CKGR_PLLBCOUNT</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_PLLBCOUNT">AT91C_CKGR_PLLBCOUNT</a></font></td><td><b>PLL B Counter</b><br>Specifies the number of slow clock cycles before the LOCKB bit is set in APMC_SR after APMC_PLLB is written.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="CKGR_OUTB"></a><b>CKGR_OUTB</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTB">AT91C_CKGR_OUTB</a></font></td><td><b>PLL B Output Frequency Range</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_OUTB_0"></a><b>CKGR_OUTB_0</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTB_0">AT91C_CKGR_OUTB_0</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_OUTB_1"></a><b>CKGR_OUTB_1</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTB_1">AT91C_CKGR_OUTB_1</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="CKGR_OUTB_2"></a><b>CKGR_OUTB_2</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTB_2">AT91C_CKGR_OUTB_2</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="CKGR_OUTB_3"></a><b>CKGR_OUTB_3</b><font size="-1"><br><a href="AT91RM9200_h.html#AT91C_CKGR_OUTB_3">AT91C_CKGR_OUTB_3</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">26..16</td><td align="CENTER"><a name="CKGR_MULB"></a><b>CKGR_MULB</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_MULB">AT91C_CKGR_MULB</a></font></td><td><b>PLL B Multiplier</b><br>0 = The PLL B is deactivated.<br>1 up to 2047 = The PLL B output frequency is the PLL B input frequency multiplied by MULB + 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">28</td><td align="CENTER"><a name="CKGR_USB_96M"></a><b>CKGR_USB_96M</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_USB_96M">AT91C_CKGR_USB_96M</a></font></td><td><b>Divider for USB Ports</b><br>0 = USB 48 MHz clock is PLL B output, therefore PLL B output must be programmed at 48 MHz.<br>1 = USB 48 MHz clock is PLL B output divided by 2, therefore PLL B output must be programmed at 96 MHz.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">29</td><td align="CENTER"><a name="CKGR_USB_PLL"></a><b>CKGR_USB_PLL</b><font size="-2"><br><a href="AT91RM9200_h.html#AT91C_CKGR_USB_PLL">AT91C_CKGR_USB_PLL</a></font></td><td><b>PLL Use</b><br>0 = PLL B is not used to drive the USB Ports. However, PLLB output can be used to drive pckx and/or processor clock.<br>1 = PLL B is used to drive the USB Ports.<br>Note: If system clock is PLL B output, USB_PLL must be reset permanently.</td></tr>
</null></table>
</null><hr></html>
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