; 17                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------------------------------------------------+
; Estimated Delay Added for Hold Timing                      ;
+-----------------+----------------------+-------------------+
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+-----------------+----------------------+-------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                    ;
+--------------------------------------------------------------------------------+---------+
; Name                                                                           ; Value   ;
+--------------------------------------------------------------------------------+---------+
; Mid Wire Use - Fit Attempt 1                                                   ; 13      ;
; Mid Slack - Fit Attempt 1                                                      ; -10551  ;
; Internal Atom Count - Fit Attempt 1                                            ; 54      ;
; LE/ALM Count - Fit Attempt 1                                                   ; 54      ;
; LAB Count - Fit Attempt 1                                                      ; 8       ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.750   ;
; Inputs per LAB - Fit Attempt 1                                                 ; 6.625   ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.875   ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:8     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:8     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:8     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:8     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:8     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:8     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:8     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:8     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:8     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:7 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:7 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:8     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:7 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:5;1:3 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:3;1:5 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:5;1:3 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:8     ;
; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1                    ; 1:8     ;
; LEs in Chains - Fit Attempt 1                                                  ; 25      ;
; LEs in Long Chains - Fit Attempt 1                                             ; 25      ;
; LABs with Chains - Fit Attempt 1                                               ; 3       ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0       ;
; Time - Fit Attempt 1                                                           ; 0       ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016   ;
+--------------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Wire Use - Fit Attempt 1      ; 2     ;
; Early Slack - Fit Attempt 1         ; -9609 ;
; Mid Wire Use - Fit Attempt 1        ; 5     ;
; Mid Slack - Fit Attempt 1           ; -8936 ;
; Mid Wire Use - Fit Attempt 1        ; 5     ;
; Mid Slack - Fit Attempt 1           ; -8242 ;
; Late Wire Use - Fit Attempt 1       ; 5     ;
; Late Slack - Fit Attempt 1          ; -8242 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000 ;
; Time - Fit Attempt 1                ; 1     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.125 ;
+-------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -7735 ;
; Early Wire Use - Fit Attempt 1      ; 4     ;
; Peak Regional Wire - Fit Attempt 1  ; 4     ;
; Mid Slack - Fit Attempt 1           ; -8766 ;
; Late Slack - Fit Attempt 1          ; -8766 ;
; Late Wire Use - Fit Attempt 1       ; 5     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.063 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Sun Sep 11 14:48:17 2011
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ledwater -c ledwater
Info: Only one processor detected - disabling parallel compilation
Info: Selected device EPM240T100C5 for design "ledwater"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM240T100A5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
    Info: Device EPM570T100A5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk_50M" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing
Info: Fitter preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 8.533 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y2; Fanout = 3; REG Node = 'count[6]'
    Info: 2: + IC(0.919 ns) + CELL(0.914 ns) = 1.833 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'Equal0~1'
    Info: 3: + IC(1.534 ns) + CELL(0.740 ns) = 4.107 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'Equal0~4'
    Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 5.287 ns; Loc. = LAB_X5_Y1; Fanout = 14; COMB Node = 'Equal0~7'
    Info: 5: + IC(2.655 ns) + CELL(0.591 ns) = 8.533 ns; Loc. = LAB_X7_Y2; Fanout = 4; REG Node = 'count[22]'
    Info: Total cell delay = 3.159 ns ( 37.02 % )
    Info: Total interconnect delay = 5.374 ns ( 62.98 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources
    Info: Peak interconnect usage is 3% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Generated suppressed messages file E:/CPLD學(xué)習(xí)資料/Verilog參考例程/3、分頻1秒/ledwater.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 191 megabytes
    Info: Processing ended: Sun Sep 11 14:48:25 2011
    Info: Elapsed time: 00:00:08
    Info: Total CPU time (on all processors): 00:00:04


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/CPLD學(xué)習(xí)資料/Verilog參考例程/3、分頻1秒/ledwater.fit.smsg.