#define XM_MD_RX_CRCE	(1L<<8)		/* Bit  8:	Rx CRC Error Frame */#define XM_MD_RX_ERR	(1L<<7)		/* Bit  7:	Rx Error Frame */#define XM_MD_DIS_UC	(1L<<6)		/* Bit  6:	Disable Rx Unicast */#define XM_MD_DIS_MC	(1L<<5)		/* Bit  5:	Disable Rx Multicast */#define XM_MD_DIS_BC	(1L<<4)		/* Bit  4:	Disable Rx Broadcast */#define XM_MD_ENA_PROM	(1L<<3)		/* Bit  3:	Enable Promiscuous */#define XM_MD_ENA_BE	(1L<<2)		/* Bit  2:	Enable Big Endian */#define XM_MD_FTF		(1L<<1)		/* Bit  1: (sc)	Flush Tx FIFO */#define XM_MD_FRF		(1L<<0)		/* Bit  0: (sc)	Flush Rx FIFO */#define XM_PAUSE_MODE	(XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)#define XM_DEF_MODE		(XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\				XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)/*	XM_STAT_CMD	16 bit r/w	Statistics Command Register */								/* Bit 16..6:	reserved */#define XM_SC_SNP_RXC	(1<<5)	/* Bit  5: (sc)	Snap Rx Counters */#define XM_SC_SNP_TXC	(1<<4)	/* Bit  4: (sc)	Snap Tx Counters */#define XM_SC_CP_RXC	(1<<3)	/* Bit  3: 	Copy Rx Counters Continuously */#define XM_SC_CP_TXC	(1<<2)	/* Bit  2:	Copy Tx Counters Continuously */#define XM_SC_CLR_RXC	(1<<1)	/* Bit  1: (sc)	Clear Rx Counters */#define XM_SC_CLR_TXC	(1<<0)	/* Bit  0: (sc) Clear Tx Counters *//*	XM_RX_CNT_EV	32 bit r/o	Rx Counter Event Register *//*	XM_RX_EV_MSK	32 bit r/w	Rx Counter Event Mask */#define XMR_MAX_SZ_OV	(1UL<<31)	/* Bit 31:	1024-MaxSize Rx Cnt Ov*/#define XMR_1023B_OV	(1L<<30)	/* Bit 30:	512-1023Byte Rx Cnt Ov*/#define XMR_511B_OV		(1L<<29)	/* Bit 29:	256-511 Byte Rx Cnt Ov*/#define XMR_255B_OV		(1L<<28)	/* Bit 28:	128-255 Byte Rx Cnt Ov*/#define XMR_127B_OV		(1L<<27)	/* Bit 27:	65-127 Byte Rx Cnt Ov */#define XMR_64B_OV		(1L<<26)	/* Bit 26:	64 Byte Rx Cnt Ov */#define XMR_UTIL_OV		(1L<<25)	/* Bit 25:	Rx Util Cnt Overflow */#define XMR_UTIL_UR		(1L<<24)	/* Bit 24:	Rx Util Cnt Underrun */#define XMR_CEX_ERR_OV	(1L<<23)	/* Bit 23:	CEXT Err Cnt Ov */									/* Bit 22:	reserved */#define XMR_FCS_ERR_OV	(1L<<21)	/* Bit 21:	Rx FCS Error Cnt Ov */#define XMR_LNG_ERR_OV	(1L<<20)	/* Bit 20:	Rx too Long Err Cnt Ov*/#define XMR_RUNT_OV		(1L<<19)	/* Bit 19:	Runt Event Cnt Ov */#define XMR_SHT_ERR_OV	(1L<<18)	/* Bit 18:	Rx Short Ev Err Cnt Ov*/#define XMR_SYM_ERR_OV	(1L<<17)	/* Bit 17:	Rx Sym Err Cnt Ov */									/* Bit 16:	reserved */#define XMR_CAR_ERR_OV	(1L<<15)	/* Bit 15:	Rx Carr Ev Err Cnt Ov */#define XMR_JAB_PKT_OV	(1L<<14)	/* Bit 14:	Rx Jabb Packet Cnt Ov */#define XMR_FIFO_OV		(1L<<13)	/* Bit 13:	Rx FIFO Ov Ev Cnt Ov */#define XMR_FRA_ERR_OV	(1L<<12)	/* Bit 12:	Rx Framing Err Cnt Ov */#define XMR_FMISS_OV	(1L<<11)	/* Bit 11:	Rx Missed Ev Cnt Ov */#define XMR_BURST		(1L<<10)	/* Bit 10:	Rx Burst Event Cnt Ov */#define XMR_INV_MOC		(1L<<9)		/* Bit  9:	Rx with inv. MAC OC Ov*/#define XMR_INV_MP		(1L<<8)		/* Bit  8:	Rx inv Pause Frame Ov */#define XMR_MCTRL_OV	(1L<<7)		/* Bit  7:	Rx MAC Ctrl-F Cnt Ov */#define XMR_MPAUSE_OV	(1L<<6)		/* Bit  6:	Rx Pause MAC Ctrl-F Ov*/#define XMR_UC_OK_OV	(1L<<5)		/* Bit  5:	Rx Unicast Frame CntOv*/#define XMR_MC_OK_OV	(1L<<4)		/* Bit  4:	Rx Multicast Cnt Ov */#define XMR_BC_OK_OV	(1L<<3)		/* Bit  3:	Rx Broadcast Cnt Ov */#define XMR_OK_LO_OV	(1L<<2)		/* Bit  2:	Octets Rx OK Low CntOv*/#define XMR_OK_HI_OV	(1L<<1)		/* Bit  1:	Octets Rx OK Hi Cnt Ov*/#define XMR_OK_OV		(1L<<0)		/* Bit  0:	Frames Received Ok Ov */#define XMR_DEF_MSK		(XMR_OK_LO_OV | XMR_OK_HI_OV)/*	XM_TX_CNT_EV	32 bit r/o	Tx Counter Event Register *//*	XM_TX_EV_MSK	32 bit r/w	Tx Counter Event Mask */									/* Bit 31..26:	reserved */#define XMT_MAX_SZ_OV	(1L<<25)	/* Bit 25:	1024-MaxSize Tx Cnt Ov*/#define XMT_1023B_OV	(1L<<24)	/* Bit 24:	512-1023Byte Tx Cnt Ov*/#define XMT_511B_OV		(1L<<23)	/* Bit 23:	256-511 Byte Tx Cnt Ov*/#define XMT_255B_OV		(1L<<22)	/* Bit 22:	128-255 Byte Tx Cnt Ov*/#define XMT_127B_OV		(1L<<21)	/* Bit 21:	65-127 Byte Tx Cnt Ov */#define XMT_64B_OV		(1L<<20)	/* Bit 20:	64 Byte Tx Cnt Ov */#define XMT_UTIL_OV		(1L<<19)	/* Bit 19:	Tx Util Cnt Overflow */#define XMT_UTIL_UR		(1L<<18)	/* Bit 18:	Tx Util Cnt Underrun */#define XMT_CS_ERR_OV	(1L<<17)	/* Bit 17:	Tx Carr Sen Err Cnt Ov*/#define XMT_FIFO_UR_OV	(1L<<16)	/* Bit 16:	Tx FIFO Ur Ev Cnt Ov */#define XMT_EX_DEF_OV	(1L<<15)	/* Bit 15:	Tx Ex Deferall Cnt Ov */#define XMT_DEF			(1L<<14)	/* Bit 14:	Tx Deferred Cnt Ov */#define XMT_LAT_COL_OV	(1L<<13)	/* Bit 13:	Tx Late Col Cnt Ov */#define XMT_ABO_COL_OV	(1L<<12)	/* Bit 12:	Tx abo dueto Ex Col Ov*/#define XMT_MUL_COL_OV	(1L<<11)	/* Bit 11:	Tx Mult Col Cnt Ov */#define XMT_SNG_COL		(1L<<10)	/* Bit 10:	Tx Single Col Cnt Ov */#define XMT_MCTRL_OV	(1L<<9)		/* Bit  9:	Tx MAC Ctrl Counter Ov*/#define XMT_MPAUSE		(1L<<8)		/* Bit  8:	Tx Pause MAC Ctrl-F Ov*/#define XMT_BURST		(1L<<7)		/* Bit  7:	Tx Burst Event Cnt Ov */#define XMT_LONG		(1L<<6)		/* Bit  6:	Tx Long Frame Cnt Ov */#define XMT_UC_OK_OV	(1L<<5)		/* Bit  5:	Tx Unicast Cnt Ov */#define XMT_MC_OK_OV	(1L<<4)		/* Bit  4:	Tx Multicast Cnt Ov */#define XMT_BC_OK_OV	(1L<<3)		/* Bit  3:	Tx Broadcast Cnt Ov */#define XMT_OK_LO_OV	(1L<<2)		/* Bit  2:	Octets Tx OK Low CntOv*/#define XMT_OK_HI_OV	(1L<<1)		/* Bit  1:	Octets Tx OK Hi Cnt Ov*/#define XMT_OK_OV		(1L<<0)		/* Bit  0:	Frames Tx Ok Ov */#define XMT_DEF_MSK		(XMT_OK_LO_OV | XMT_OK_HI_OV)/* * Receive Frame Status Encoding */#define XMR_FS_LEN	(0x3fffUL<<18)	/* Bit 31..18:	Rx Frame Length */#define XMR_FS_2L_VLAN	(1L<<17)	/* Bit 17:	tagged wh 2Lev VLAN ID*/#define XMR_FS_1L_VLAN	(1L<<16)	/* Bit 16:	tagged wh 1Lev VLAN ID*/#define XMR_FS_BC		(1L<<15)	/* Bit 15:	Broadcast Frame */#define XMR_FS_MC		(1L<<14)	/* Bit 14:	Multicast Frame */#define XMR_FS_UC		(1L<<13)	/* Bit 13:	Unicast Frame */									/* Bit 12:	reserved */#define XMR_FS_BURST	(1L<<11)	/* Bit 11:	Burst Mode */#define XMR_FS_CEX_ERR	(1L<<10)	/* Bit 10:	Carrier Ext. Error */#define XMR_FS_802_3	(1L<<9)		/* Bit  9:	802.3 Frame */#define XMR_FS_COL_ERR	(1L<<8)		/* Bit  8:	Collision Error */#define XMR_FS_CAR_ERR	(1L<<7)		/* Bit  7:	Carrier Event Error */#define XMR_FS_LEN_ERR	(1L<<6)		/* Bit  6:	In-Range Length Error */#define XMR_FS_FRA_ERR	(1L<<5)		/* Bit  5:	Framing Error */#define XMR_FS_RUNT		(1L<<4)		/* Bit  4:	Runt Frame */#define XMR_FS_LNG_ERR	(1L<<3)		/* Bit  3:	Giant (Jumbo) Frame */#define XMR_FS_FCS_ERR	(1L<<2)		/* Bit  2:	Frame Check Sequ Err */#define XMR_FS_ERR		(1L<<1)		/* Bit  1:	Frame Error */#define XMR_FS_MCTRL	(1L<<0)		/* Bit  0:	MAC Control Packet *//* * XMR_FS_ERR will be set if *	XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, *	XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue * XMR_FS_ERR unless the corresponding bit in the Receive Command * Register is set. */#define XMR_FS_ANY_ERR	XMR_FS_ERR/*----------------------------------------------------------------------------*//* * XMAC-PHY Registers, indirect addressed over the XMAC */#define PHY_XMAC_CTRL		0x00	/* 16 bit r/w	PHY Control Register */#define PHY_XMAC_STAT		0x01	/* 16 bit r/w	PHY Status Register */#define PHY_XMAC_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */#define PHY_XMAC_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */#define PHY_XMAC_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */#define PHY_XMAC_AUNE_LP	0x05	/* 16 bit r/o	Link Partner Abi Reg */#define PHY_XMAC_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */#define PHY_XMAC_NEPG		0x07	/* 16 bit r/w	Next Page Register */#define PHY_XMAC_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link P Reg */	/* 0x09 - 0x0e:		reserved */#define PHY_XMAC_EXT_STAT	0x0f	/* 16 bit r/o	Ext Status Register */#define PHY_XMAC_RES_ABI	0x10	/* 16 bit r/o	PHY Resolved Ability *//*----------------------------------------------------------------------------*//* * Broadcom-PHY Registers, indirect addressed over XMAC */#define PHY_BCOM_CTRL		0x00	/* 16 bit r/w	PHY Control Register */#define PHY_BCOM_STAT		0x01	/* 16 bit r/o	PHY Status Register */#define PHY_BCOM_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */#define PHY_BCOM_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */#define PHY_BCOM_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */#define PHY_BCOM_AUNE_LP	0x05	/* 16 bit r/o	Link Part Ability Reg */#define PHY_BCOM_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */#define PHY_BCOM_NEPG		0x07	/* 16 bit r/w	Next Page Register */#define PHY_BCOM_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link P Reg */	/* Broadcom-specific registers */#define PHY_BCOM_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Ctrl Reg */#define PHY_BCOM_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */	/* 0x0b - 0x0e:		reserved */#define PHY_BCOM_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Reg */#define PHY_BCOM_P_EXT_CTRL	0x10	/* 16 bit r/w	PHY Extended Ctrl Reg */#define PHY_BCOM_P_EXT_STAT	0x11	/* 16 bit r/o	PHY Extended Stat Reg */#define PHY_BCOM_RE_CTR		0x12	/* 16 bit r/w	Receive Error Counter */#define PHY_BCOM_FC_CTR		0x13	/* 16 bit r/w	False Carr Sense Cnt */#define PHY_BCOM_RNO_CTR	0x14	/* 16 bit r/w	Receiver NOT_OK Cnt */	/* 0x15 - 0x17:		reserved */#define PHY_BCOM_AUX_CTRL	0x18	/* 16 bit r/w	Auxiliary Control Reg */#define PHY_BCOM_AUX_STAT	0x19	/* 16 bit r/o	Auxiliary Stat Summary */#define PHY_BCOM_INT_STAT	0x1a	/* 16 bit r/o	Interrupt Status Reg */#define PHY_BCOM_INT_MASK	0x1b	/* 16 bit r/w	Interrupt Mask Reg */	/* 0x1c:		reserved */	/* 0x1d - 0x1f:		test registers *//*----------------------------------------------------------------------------*//* * Marvel-PHY Registers, indirect addressed over GMAC */#define PHY_MARV_CTRL		0x00	/* 16 bit r/w	PHY Control Register */#define PHY_MARV_STAT		0x01	/* 16 bit r/o	PHY Status Register */#define PHY_MARV_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */#define PHY_MARV_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */#define PHY_MARV_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */#define PHY_MARV_AUNE_LP	0x05	/* 16 bit r/o	Link Part Ability Reg */#define PHY_MARV_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */#define PHY_MARV_NEPG		0x07	/* 16 bit r/w	Next Page Register */#define PHY_MARV_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link P Reg */	/* Marvel-specific registers */#define PHY_MARV_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Ctrl Reg */#define PHY_MARV_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */	/* 0x0b - 0x0e:		reserved */#define PHY_MARV_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Reg */#define PHY_MARV_PHY_CTRL	0x10	/* 16 bit r/w	PHY Specific Ctrl Reg */#define PHY_MARV_PHY_STAT	0x11	/* 16 bit r/o	PHY Specific Stat Reg */#define PHY_MARV_INT_MASK	0x12	/* 16 bit r/w	Interrupt Mask Reg */#define PHY_MARV_INT_STAT	0x13	/* 16 bit r/o	Interrupt Status Reg */#define PHY_MARV_EXT_CTRL	0x14	/* 16 bit r/w	Ext. PHY Specific Ctrl */#define PHY_MARV_RXE_CNT	0x15	/* 16 bit r/w	Receive Error Counter */#define PHY_MARV_EXT_ADR	0x16	/* 16 bit r/w	Ext. Ad. for Cable Diag. */	/* 0x17:		reserved */#define PHY_MARV_LED_CTRL	0x18	/* 16 bit r/w	LED Control Reg */#define PHY_MARV_LED_OVER	0x19	/* 16 bit r/w	Manual LED Override Reg */#define PHY_MARV_EXT_CTRL_2	0x1a	/* 16 bit r/w	Ext. PHY Specific Ctrl 2 */#define PHY_MARV_EXT_P_STAT	0x1b	/* 16 bit r/w	Ext. PHY Spec. Stat Reg */#define PHY_MARV_CABLE_DIAG	0x1c	/* 16 bit r/o	Cable Diagnostic Reg */	/* 0x1d - 0x1f:		reserved *//*----------------------------------------------------------------------------*//* * Level One-PHY Registers, indirect addressed over XMAC */#define PHY_LONE_CTRL		0x00	/* 16 bit r/w	PHY Control Register */#define PHY_LONE_STAT		0x01	/* 16 bit r/o	PHY Status Register */#define PHY_LONE_ID0		0x02	/* 16 bit r/o	PHY ID0 Register */#define PHY_LONE_ID1		0x03	/* 16 bit r/o	PHY ID1 Register */#define PHY_LONE_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */#define PHY_LONE_AUNE_LP	0x05	/* 16 bit r/o	Link Part Ability Reg */#define PHY_LONE_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */#define PHY_LONE_NEPG		0x07	/* 16 bit r/w	Next Page Register */#define PHY_LONE_NEPG_LP	0x08	/* 16 bit r/o	Next Page Link Partner*/	/* Level One-specific registers */#define PHY_LONE_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg*/#define PHY_LONE_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */	/* 0x0b -0x0e:		reserved */#define PHY_LONE_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Reg */#define PHY_LONE_PORT_CFG	0x10	/* 16 bit r/w	Port Configuration Reg*/#define PHY_LONE_Q_STAT		0x11	/* 16 bit r/o	Quick Status Reg */#define PHY_LONE_INT_ENAB	0x12	/* 16 bit r/w	Interrupt Enable Reg */#define PHY_LONE_INT_STAT	0x13	/* 16 bit r/o	Interrupt Status Reg */#define PHY_LONE_LED_CFG	0x14	/* 16 bit r/w	LED Configuration Reg */#define PHY_LONE_PORT_CTRL	0x15	/* 16 bit r/w	Port Control Reg */#define PHY_LONE_CIM		0x16	/* 16 bit r/o	CIM Reg */	/* 0x17 -0x1c:		reserved *//*----------------------------------------------------------------------------*//* * National-PHY Registers, indirect addressed over XMAC */#define PHY_NAT_CTRL		0x00	/* 16 bit r/w	PHY Control Register */#define PHY_NAT_STAT		0x01	/* 16 bit r/w	PHY Status Register */#define PHY_NAT_ID0			0x02	/* 16 bit r/o	PHY ID0 Register */#define PHY_NAT_ID1			0x03	/* 16 bit r/o	PHY ID1 Register */#define PHY_NAT_AUNE_ADV	0x04	/* 16 bit r/w	Auto-Neg. Advertisement */#define PHY_NAT_AUNE_LP		0x05	/* 16 bit r/o	Link Partner Ability Reg */#define PHY_NAT_AUNE_EXP	0x06	/* 16 bit r/o	Auto-Neg. Expansion Reg */#define PHY_NAT_NEPG		0x07	/* 16 bit r/w	Next Page Register */#define PHY_NAT_NEPG_LP		0x08	/* 16 bit r/o	Next Page Link Partner Reg */	/* National-specific registers */#define PHY_NAT_1000T_CTRL	0x09	/* 16 bit r/w	1000Base-T Control Reg */#define PHY_NAT_1000T_STAT	0x0a	/* 16 bit r/o	1000Base-T Status Reg */	/* 0x0b -0x0e:		reserved */#define PHY_NAT_EXT_STAT	0x0f	/* 16 bit r/o	Extended Status Register */#define PHY_NAT_EXT_CTRL1	0x10	/* 16 bit r/o	Extended Control Reg1 */#define PHY_NAT_Q_STAT1		0x11	/* 16 bit r/o	Quick Status Reg1 */#define PHY_NAT_10B_OP		0x12	/* 16 bit r/o	10Base-T Operations Reg */#define PHY_NAT_EXT_CTRL2	0x13	/* 16 bit r/o	Extended Control Reg1 */#define PHY_NAT_Q_STAT2		0x14	/* 16 bit r/o	Quick Status Reg2 */	/* 0x15 -0x18:		reserved */#define PHY_NAT_PHY_ADDR	0x19	/* 16 bit r/o	PHY Address Register *//*----------------------------------------------------------------------------*//* * PHY bit definitions * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are