?? stm8s_uart2.ls
字號:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Generator V4.2.8 - 03 Dec 2008
43 ; 48 void UART2_DeInit(void)
43 ; 49 {
45 switch .text
46 0000 _UART2_DeInit:
48 0000 88 push a
49 00000001 OFST: set 1
52 ; 50 u8 dummy = 0;
54 0001 0f01 clr (OFST+0,sp)
55 ; 53 dummy = UART2->SR;
57 0003 c65240 ld a,21056
58 0006 6b01 ld (OFST+0,sp),a
59 ; 54 dummy = UART2->DR;
61 0008 c65241 ld a,21057
62 000b 6b01 ld (OFST+0,sp),a
63 ; 56 UART2->BRR2 = UART2_BRR2_RESET_VALUE; /*< Set UART2_BRR2 to reset value 0x00 */
65 000d 725f5243 clr 21059
66 ; 57 UART2->BRR1 = UART2_BRR1_RESET_VALUE; /*< Set UART2_BRR1 to reset value 0x00 */
68 0011 725f5242 clr 21058
69 ; 59 UART2->CR1 = UART2_CR1_RESET_VALUE; /*< Set UART2_CR1 to reset value 0x00 */
71 0015 725f5244 clr 21060
72 ; 60 UART2->CR2 = UART2_CR2_RESET_VALUE; /*< Set UART2_CR2 to reset value 0x00 */
74 0019 725f5245 clr 21061
75 ; 61 UART2->CR3 = UART2_CR3_RESET_VALUE; /*< Set UART2_CR3 to reset value 0x00 */
77 001d 725f5246 clr 21062
78 ; 62 UART2->CR4 = UART2_CR4_RESET_VALUE; /*< Set UART2_CR4 to reset value 0x00 */
80 0021 725f5247 clr 21063
81 ; 63 UART2->CR5 = UART2_CR5_RESET_VALUE; /*< Set UART2_CR5 to reset value 0x00 */
84 ; 64 UART2->CR6 = UART2_CR6_RESET_VALUE; /*< Set UART2_CR6 to reset value 0x00 */
86 0029 725f5249 clr 21065
87 ; 66 }
90 002d 84 pop a
91 002e 81 ret
412 .const: section .text
413 0000 L01:
414 0000 00000064 dc.l 100
415 ; 78 void UART2_Init(u32 BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
415 ; 79 {
416 switch .text
417 002f _UART2_Init:
419 002f 520e subw sp,#14
420 0000000e OFST: set 14
423 ; 80 u8 BRR2_1, BRR2_2 = 0;
425 0031 7b06 ld a,(OFST-8,sp)
426 0033 97 ld xl,a
427 ; 81 u32 BaudRate_Mantissa, BaudRate_Mantissa100 = 0;
429 0034 96 ldw x,sp
430 0035 1c0007 addw x,#OFST-7
431 0038 cd0000 call c_ltor
433 ; 84 assert_param(IS_UART2_BAUDRATE_OK(BaudRate));
435 ; 86 assert_param(IS_UART2_WORDLENGTH_OK(WordLength));
437 ; 88 assert_param(IS_UART2_STOPBITS_OK(StopBits));
439 ; 90 assert_param(IS_UART2_PARITY_OK(Parity));
441 ; 93 assert_param(IS_UART2_MODE_OK((u8)Mode));
443 ; 97 assert_param(IS_UART2_SYNCMODE_OK((u8)SyncMode));
445 ; 99 UART2->CR1 &= (u8)(~UART2_CR1_M); /**< Clear the word length bit */
447 003b 72195244 bres 21060,#4
448 ; 100 UART2->CR1 |= (u8)WordLength; /**< Set the word length bit according to UART2_WordLength value */
450 003f c65244 ld a,21060
451 0042 1a15 or a,(OFST+7,sp)
452 0044 c75244 ld 21060,a
453 ; 102 UART2->CR3 &= (u8)(~UART2_CR3_STOP); /**< Clear the STOP bits */
455 0047 c65246 ld a,21062
456 004a a4cf and a,#207
457 004c c75246 ld 21062,a
458 ; 103 UART2->CR3 |= (u8)StopBits; /**< Set the STOP bits number according to UART2_StopBits value */
460 004f c65246 ld a,21062
461 0052 1a16 or a,(OFST+8,sp)
462 0054 c75246 ld 21062,a
463 ; 105 UART2->CR1 &= (u8)(~(UART2_CR1_PCEN | UART2_CR1_PS )); /**< Clear the Parity Control bit */
465 0057 c65244 ld a,21060
466 005a a4f9 and a,#249
467 005c c75244 ld 21060,a
468 ; 106 UART2->CR1 |= (u8)Parity; /**< Set the Parity Control bit to UART2_Parity value */
470 005f c65244 ld a,21060
471 0062 1a17 or a,(OFST+9,sp)
472 0064 c75244 ld 21060,a
473 ; 108 UART2->BRR1 &= (u8)(~UART2_BRR1_DIVM); /**< Clear the LSB mantissa of UARTDIV */
475 0067 725f5242 clr 21058
476 ; 109 UART2->BRR2 &= (u8)(~UART2_BRR2_DIVM); /**< Clear the MSB mantissa of UARTDIV */
478 006b c65243 ld a,21059
479 006e a40f and a,#15
480 0070 c75243 ld 21059,a
481 ; 110 UART2->BRR2 &= (u8)(~UART2_BRR2_DIVF); /**< Clear the Fraction bits of UARTDIV */
483 0073 c65243 ld a,21059
484 0076 a4f0 and a,#240
485 0078 c75243 ld 21059,a
486 ; 113 BaudRate_Mantissa = ((u32)CLK_GetClockFreq() / (BaudRate << 4));
488 007b 96 ldw x,sp
489 007c 1c0011 addw x,#OFST+3
490 007f cd0000 call c_ltor
492 0082 a604 ld a,#4
493 0084 cd0000 call c_llsh
495 0087 96 ldw x,sp
496 0088 1c0001 addw x,#OFST-13
497 008b cd0000 call c_rtol
499 008e cd0000 call _CLK_GetClockFreq
501 0091 96 ldw x,sp
502 0092 1c0001 addw x,#OFST-13
503 0095 cd0000 call c_ludv
505 0098 96 ldw x,sp
506 0099 1c000b addw x,#OFST-3
507 009c cd0000 call c_rtol
509 ; 114 BaudRate_Mantissa100 = (((u32)CLK_GetClockFreq() * 100) / (BaudRate << 4));
511 009f 96 ldw x,sp
512 00a0 1c0011 addw x,#OFST+3
513 00a3 cd0000 call c_ltor
515 00a6 a604 ld a,#4
516 00a8 cd0000 call c_llsh
518 00ab 96 ldw x,sp
519 00ac 1c0001 addw x,#OFST-13
520 00af cd0000 call c_rtol
522 00b2 cd0000 call _CLK_GetClockFreq
524 00b5 a664 ld a,#100
525 00b7 cd0000 call c_smul
527 00ba 96 ldw x,sp
528 00bb 1c0001 addw x,#OFST-13
529 00be cd0000 call c_ludv
531 00c1 96 ldw x,sp
532 00c2 1c0007 addw x,#OFST-7
533 00c5 cd0000 call c_rtol
535 ; 116 BRR2_1 = (u8)((u8)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
535 ; 117 << 4) / 100) & (u8)0x0F); /**< Set the fraction of UARTDIV */
537 00c8 96 ldw x,sp
538 00c9 1c000b addw x,#OFST-3
539 00cc cd0000 call c_ltor
541 00cf a664 ld a,#100
542 00d1 cd0000 call c_smul
544 00d4 96 ldw x,sp
545 00d5 1c0001 addw x,#OFST-13
546 00d8 cd0000 call c_rtol
548 00db 96 ldw x,sp
549 00dc 1c0007 addw x,#OFST-7
550 00df cd0000 call c_ltor
552 00e2 96 ldw x,sp
553 00e3 1c0001 addw x,#OFST-13
554 00e6 cd0000 call c_lsub
556 00e9 a604 ld a,#4
557 00eb cd0000 call c_llsh
559 00ee ae0000 ldw x,#L01
560 00f1 cd0000 call c_ludv
562 00f4 b603 ld a,c_lreg+3
563 00f6 a40f and a,#15
564 00f8 6b05 ld (OFST-9,sp),a
565 ; 118 BRR2_2 = (u8)((BaudRate_Mantissa >> 4) & (u8)0xF0);
567 00fa 96 ldw x,sp
568 00fb 1c000b addw x,#OFST-3
569 00fe cd0000 call c_ltor
571 0101 a604 ld a,#4
572 0103 cd0000 call c_lursh
574 0106 b603 ld a,c_lreg+3
575 0108 a4f0 and a,#240
576 010a b703 ld c_lreg+3,a
577 010c 3f02 clr c_lreg+2
578 010e 3f01 clr c_lreg+1
579 0110 3f00 clr c_lreg
580 0112 b603 ld a,c_lreg+3
581 0114 6b06 ld (OFST-8,sp),a
582 ; 120 UART2->BRR2 = (u8)(BRR2_1 | BRR2_2);
584 0116 7b05 ld a,(OFST-9,sp)
585 0118 1a06 or a,(OFST-8,sp)
586 011a c75243 ld 21059,a
587 ; 121 UART2->BRR1 = (u8)BaudRate_Mantissa; /**< Set the LSB mantissa of UARTDIV */
589 011d 7b0e ld a,(OFST+0,sp)
590 011f c75242 ld 21058,a
591 ; 123 UART2->CR2 &= (u8)~(UART2_CR2_TEN | UART2_CR2_REN); /**< Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */
593 0122 c65245 ld a,21061
594 0125 a4f3 and a,#243
595 0127 c75245 ld 21061,a
596 ; 124 UART2->CR3 &= (u8)~(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL); /**< Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
598 012a c65246 ld a,21062
599 012d a4f8 and a,#248
600 012f c75246 ld 21062,a
601 ; 125 UART2->CR3 |= (u8)((u8)SyncMode & (u8)(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL)); /**< Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
603 0132 7b18 ld a,(OFST+10,sp)
604 0134 a407 and a,#7
605 0136 ca5246 or a,21062
606 0139 c75246 ld 21062,a
607 ; 127 if ((u8)Mode & (u8)UART2_MODE_TX_ENABLE)
609 013c 7b19 ld a,(OFST+11,sp)
610 013e a504 bcp a,#4
611 0140 2706 jreq L112
612 ; 129 UART2->CR2 |= (u8)UART2_CR2_TEN; /**< Set the Transmitter Enable bit */
614 0142 72165245 bset 21061,#3
616 0146 2004 jra L312
617 0148 L112:
618 ; 133 UART2->CR2 &= (u8)(~UART2_CR2_TEN); /**< Clear the Transmitter Disable bit */
620 0148 72175245 bres 21061,#3
621 014c L312:
622 ; 135 if ((u8)Mode & (u8)UART2_MODE_RX_ENABLE)
624 014c 7b19 ld a,(OFST+11,sp)
625 014e a508 bcp a,#8
626 0150 2706 jreq L512
627 ; 137 UART2->CR2 |= (u8)UART2_CR2_REN; /**< Set the Receiver Enable bit */
629 0152 72145245 bset 21061,#2
631 0156 2004 jra L712
632 0158 L512:
633 ; 141 UART2->CR2 &= (u8)(~UART2_CR2_REN); /**< Clear the Receiver Disable bit */
635 0158 72155245 bres 21061,#2
636 015c L712:
637 ; 144 if ((u8)SyncMode&(u8)UART2_SYNCMODE_CLOCK_DISABLE)
639 015c 7b18 ld a,(OFST+10,sp)
640 015e a580 bcp a,#128
641 0160 2706 jreq L122
642 ; 146 UART2->CR3 &= (u8)(~UART2_CR3_CKEN); /**< Clear the Clock Enable bit */
644 0162 72175246 bres 21062,#3
646 0166 200a jra L322
647 0168 L122:
648 ; 151 UART2->CR3 |= (u8)((u8)SyncMode & UART2_CR3_CKEN);
650 0168 7b18 ld a,(OFST+10,sp)
651 016a a408 and a,#8
652 016c ca5246 or a,21062
653 016f c75246 ld 21062,a
654 0172 L322:
655 ; 153 }
658 0172 5b0e addw sp,#14
659 0174 81 ret
714 ; 164 void UART2_Cmd(FunctionalState NewState)
714 ; 165 {
715 switch .text
716 0175 _UART2_Cmd:
720 ; 167 if (NewState != DISABLE)
722 0175 4d tnz a
723 0176 2706 jreq L352
724 ; 169 UART2->CR1 &= (u8)(~UART2_CR1_UARTD); /**< UART2 Enable */
726 0178 721b5244 bres 21060,#5
728 017c 2004 jra L552
729 017e L352:
730 ; 173 UART2->CR1 |= UART2_CR1_UARTD; /**< UART2 Disable (for low power consumption) */
732 017e 721a5244 bset 21060,#5
733 0182 L552:
734 ; 175 }
737 0182 81 ret
869 ; 194 void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
869 ; 195 {
870 switch .text
871 0183 _UART2_ITConfig:
873 0183 89 pushw x
874 0184 89 pushw x
875 00000002 OFST: set 2
878 ; 196 u8 uartreg, itpos = 0x00;
880 0185 7b02 ld a,(OFST+0,sp)
881 0187 97 ld xl,a
882 ; 197 assert_param(IS_UART2_CONFIG_IT_OK(UART2_IT));
884 ; 198 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
886 ; 201 uartreg = (u8)(UART2_IT >> 0x08);
888 0188 7b03 ld a,(OFST+1,sp)
889 018a 6b01 ld (OFST-1,sp),a
890 ; 204 itpos = (u8)((u8)1 << (u8)((u8)UART2_IT & (u8)0x0F));
892 018c 7b04 ld a,(OFST+2,sp)
893 018e a40f and a,#15
894 0190 5f clrw x
895 0191 97 ld xl,a
896 0192 a601 ld a,#1
897 0194 5d tnzw x
898 0195 2704 jreq L61
899 0197 L02:
900 0197 48 sll a
901 0198 5a decw x
902 0199 26fc jrne L02
903 019b L61:
904 019b 6b02 ld (OFST+0,sp),a
905 ; 206 if (NewState != DISABLE)
907 019d 0d07 tnz (OFST+5,sp)
908 019f 273a jreq L733
909 ; 209 if (uartreg == 0x01)
911 01a1 7b01 ld a,(OFST-1,sp)
912 01a3 a101 cp a,#1
913 01a5 260a jrne L143
914 ; 211 UART2->CR1 |= itpos;
916 01a7 c65244 ld a,21060
917 01aa 1a02 or a,(OFST+0,sp)
918 01ac c75244 ld 21060,a
920 01af 2066 jra L553
921 01b1 L143:
922 ; 213 else if (uartreg == 0x02)
924 01b1 7b01 ld a,(OFST-1,sp)
925 01b3 a102 cp a,#2
926 01b5 260a jrne L543
927 ; 215 UART2->CR2 |= itpos;
929 01b7 c65245 ld a,21061
930 01ba 1a02 or a,(OFST+0,sp)
931 01bc c75245 ld 21061,a
933 01bf 2056 jra L553
934 01c1 L543:
935 ; 217 else if (uartreg == 0x03)
937 01c1 7b01 ld a,(OFST-1,sp)
938 01c3 a103 cp a,#3
939 01c5 260a jrne L153
940 ; 219 UART2->CR4 |= itpos;
942 01c7 c65247 ld a,21063
943 01ca 1a02 or a,(OFST+0,sp)
944 01cc c75247 ld 21063,a
946 01cf 2046 jra L553
947 01d1 L153:
948 ; 223 UART2->CR6 |= itpos;
950 01d1 c65249 ld a,21065
951 01d4 1a02 or a,(OFST+0,sp)
952 01d6 c75249 ld 21065,a
953 01d9 203c jra L553
954 01db L733:
955 ; 229 if (uartreg == 0x01)
957 01db 7b01 ld a,(OFST-1,sp)
958 01dd a101 cp a,#1
959 01df 260b jrne L753
960 ; 231 UART2->CR1 &= (u8)(~itpos);
962 01e1 7b02 ld a,(OFST+0,sp)
963 01e3 43 cpl a
964 01e4 c45244 and a,21060
965 01e7 c75244 ld 21060,a
967 01ea 202b jra L553
968 01ec L753:
969 ; 233 else if (uartreg == 0x02)
971 01ec 7b01 ld a,(OFST-1,sp)
972 01ee a102 cp a,#2
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