?? stm8s_uart2.ls
字號:
2125 031f 81 ret
2282 ; 628 FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG)
2282 ; 629 {
2283 switch .text
2284 0320 _UART2_GetFlagStatus:
2286 0320 89 pushw x
2287 0321 88 push a
2288 00000001 OFST: set 1
2291 ; 630 FlagStatus status = RESET;
2293 0322 0f01 clr (OFST+0,sp)
2294 ; 633 assert_param(IS_UART2_FLAG_OK(UART2_FLAG));
2296 ; 636 if (UART2_FLAG == UART2_FLAG_LBDF)
2298 0324 a30210 cpw x,#528
2299 0327 2610 jrne L3611
2300 ; 638 if ((UART2->CR4 & (u8)UART2_FLAG) != (u8)0x00)
2302 0329 9f ld a,xl
2303 032a c45247 and a,21063
2304 032d 2706 jreq L5611
2305 ; 641 status = SET;
2307 032f a601 ld a,#1
2308 0331 6b01 ld (OFST+0,sp),a
2310 0333 2039 jra L1711
2311 0335 L5611:
2312 ; 646 status = RESET;
2314 0335 0f01 clr (OFST+0,sp)
2315 0337 2035 jra L1711
2316 0339 L3611:
2317 ; 649 else if (UART2_FLAG == UART2_FLAG_SBK)
2319 0339 1e02 ldw x,(OFST+1,sp)
2320 033b a30101 cpw x,#257
2321 033e 2611 jrne L3711
2322 ; 651 if ((UART2->CR2 & (u8)UART2_FLAG) != (u8)0x00)
2324 0340 c65245 ld a,21061
2325 0343 1503 bcp a,(OFST+2,sp)
2326 0345 2706 jreq L5711
2327 ; 654 status = SET;
2329 0347 a601 ld a,#1
2330 0349 6b01 ld (OFST+0,sp),a
2332 034b 2021 jra L1711
2333 034d L5711:
2334 ; 659 status = RESET;
2336 034d 0f01 clr (OFST+0,sp)
2337 034f 201d jra L1711
2338 0351 L3711:
2339 ; 662 else if ((UART2_FLAG == UART2_FLAG_LHDF) || (UART2_FLAG == UART2_FLAG_LSF))
2341 0351 1e02 ldw x,(OFST+1,sp)
2342 0353 a30302 cpw x,#770
2343 0356 2707 jreq L5021
2345 0358 1e02 ldw x,(OFST+1,sp)
2346 035a a30301 cpw x,#769
2347 035d 2614 jrne L3021
2348 035f L5021:
2349 ; 664 if ((UART2->CR6 & (u8)UART2_FLAG) != (u8)0x00)
2351 035f c65249 ld a,21065
2352 0362 1503 bcp a,(OFST+2,sp)
2353 0364 2706 jreq L7021
2354 ; 667 status = SET;
2356 0366 a601 ld a,#1
2357 0368 6b01 ld (OFST+0,sp),a
2359 036a 2002 jra L1711
2360 036c L7021:
2361 ; 672 status = RESET;
2363 036c 0f01 clr (OFST+0,sp)
2364 036e L1711:
2365 ; 690 return status;
2367 036e 7b01 ld a,(OFST+0,sp)
2370 0370 5b03 addw sp,#3
2371 0372 81 ret
2372 0373 L3021:
2373 ; 677 if ((UART2->SR & (u8)UART2_FLAG) != (u8)0x00)
2375 0373 c65240 ld a,21056
2376 0376 1503 bcp a,(OFST+2,sp)
2377 0378 2706 jreq L5121
2378 ; 680 status = SET;
2380 037a a601 ld a,#1
2381 037c 6b01 ld (OFST+0,sp),a
2383 037e 20ee jra L1711
2384 0380 L5121:
2385 ; 685 status = RESET;
2387 0380 0f01 clr (OFST+0,sp)
2388 0382 20ea jra L1711
2423 ; 718 void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG)
2423 ; 719 {
2424 switch .text
2425 0384 _UART2_ClearFlag:
2427 0384 89 pushw x
2428 00000000 OFST: set 0
2431 ; 720 assert_param(IS_UART2_CLEAR_FLAG_OK(UART2_FLAG));
2433 ; 723 if (UART2_FLAG == UART2_FLAG_RXNE)
2435 0385 a30020 cpw x,#32
2436 0388 2606 jrne L7321
2437 ; 725 UART2->SR = (u8)~(UART2_SR_RXNE);
2439 038a 35df5240 mov 21056,#223
2441 038e 201e jra L1421
2442 0390 L7321:
2443 ; 728 else if (UART2_FLAG == UART2_FLAG_LBDF)
2445 0390 1e01 ldw x,(OFST+1,sp)
2446 0392 a30210 cpw x,#528
2447 0395 2606 jrne L3421
2448 ; 730 UART2->CR4 &= (u8)(~UART2_CR4_LBDF);
2450 0397 72195247 bres 21063,#4
2452 039b 2011 jra L1421
2453 039d L3421:
2454 ; 733 else if (UART2_FLAG == UART2_FLAG_LHDF)
2456 039d 1e01 ldw x,(OFST+1,sp)
2457 039f a30302 cpw x,#770
2458 03a2 2606 jrne L7421
2459 ; 735 UART2->CR6 &= (u8)(~UART2_CR6_LHDF);
2461 03a4 72135249 bres 21065,#1
2463 03a8 2004 jra L1421
2464 03aa L7421:
2465 ; 740 UART2->CR6 &= (u8)(~UART2_CR6_LSF);
2467 03aa 72115249 bres 21065,#0
2468 03ae L1421:
2469 ; 743 }
2472 03ae 85 popw x
2473 03af 81 ret
2555 ; 761 ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT)
2555 ; 762 {
2556 switch .text
2557 03b0 _UART2_GetITStatus:
2559 03b0 89 pushw x
2560 03b1 89 pushw x
2561 00000002 OFST: set 2
2564 ; 763 ITStatus pendingbitstatus = RESET;
2566 03b2 7b02 ld a,(OFST+0,sp)
2567 03b4 97 ld xl,a
2568 ; 764 u8 itpos = 0;
2570 03b5 7b01 ld a,(OFST-1,sp)
2571 03b7 97 ld xl,a
2572 ; 765 u8 itmask1 = 0;
2574 03b8 7b02 ld a,(OFST+0,sp)
2575 03ba 97 ld xl,a
2576 ; 766 u8 itmask2 = 0;
2578 03bb 7b02 ld a,(OFST+0,sp)
2579 03bd 97 ld xl,a
2580 ; 767 u8 enablestatus = 0;
2582 03be 7b02 ld a,(OFST+0,sp)
2583 03c0 97 ld xl,a
2584 ; 770 assert_param(IS_UART2_GET_IT_OK(UART2_IT));
2586 ; 773 itpos = (u8)((u8)1 << (u8)((u8)UART2_IT & (u8)0x0F));
2588 03c1 7b04 ld a,(OFST+2,sp)
2589 03c3 a40f and a,#15
2590 03c5 5f clrw x
2591 03c6 97 ld xl,a
2592 03c7 a601 ld a,#1
2593 03c9 5d tnzw x
2594 03ca 2704 jreq L27
2595 03cc L47:
2596 03cc 48 sll a
2597 03cd 5a decw x
2598 03ce 26fc jrne L47
2599 03d0 L27:
2600 03d0 6b01 ld (OFST-1,sp),a
2601 ; 775 itmask1 = (u8)((u8)UART2_IT >> (u8)4);
2603 03d2 7b04 ld a,(OFST+2,sp)
2604 03d4 4e swap a
2605 03d5 a40f and a,#15
2606 03d7 6b02 ld (OFST+0,sp),a
2607 ; 777 itmask2 = (u8)((u8)1 << itmask1);
2609 03d9 7b02 ld a,(OFST+0,sp)
2610 03db 5f clrw x
2611 03dc 97 ld xl,a
2612 03dd a601 ld a,#1
2613 03df 5d tnzw x
2614 03e0 2704 jreq L67
2615 03e2 L001:
2616 03e2 48 sll a
2617 03e3 5a decw x
2618 03e4 26fc jrne L001
2619 03e6 L67:
2620 03e6 6b02 ld (OFST+0,sp),a
2621 ; 782 if (UART2_IT == UART2_IT_PE)
2623 03e8 1e03 ldw x,(OFST+1,sp)
2624 03ea a30100 cpw x,#256
2625 03ed 261c jrne L5131
2626 ; 785 enablestatus = (u8)((u8)UART2->CR1 & itmask2);
2628 03ef c65244 ld a,21060
2629 03f2 1402 and a,(OFST+0,sp)
2630 03f4 6b02 ld (OFST+0,sp),a
2631 ; 788 if (((UART2->SR & itpos) != (u8)0x00) && enablestatus)
2633 03f6 c65240 ld a,21056
2634 03f9 1501 bcp a,(OFST-1,sp)
2635 03fb 270a jreq L7131
2637 03fd 0d02 tnz (OFST+0,sp)
2638 03ff 2706 jreq L7131
2639 ; 791 pendingbitstatus = SET;
2641 0401 a601 ld a,#1
2642 0403 6b02 ld (OFST+0,sp),a
2644 0405 2064 jra L3231
2645 0407 L7131:
2646 ; 796 pendingbitstatus = RESET;
2648 0407 0f02 clr (OFST+0,sp)
2649 0409 2060 jra L3231
2650 040b L5131:
2651 ; 800 else if (UART2_IT == UART2_IT_LBDF)
2653 040b 1e03 ldw x,(OFST+1,sp)
2654 040d a30346 cpw x,#838
2655 0410 261c jrne L5231
2656 ; 803 enablestatus = (u8)((u8)UART2->CR4 & itmask2);
2658 0412 c65247 ld a,21063
2659 0415 1402 and a,(OFST+0,sp)
2660 0417 6b02 ld (OFST+0,sp),a
2661 ; 805 if (((UART2->CR4 & itpos) != (u8)0x00) && enablestatus)
2663 0419 c65247 ld a,21063
2664 041c 1501 bcp a,(OFST-1,sp)
2665 041e 270a jreq L7231
2667 0420 0d02 tnz (OFST+0,sp)
2668 0422 2706 jreq L7231
2669 ; 808 pendingbitstatus = SET;
2671 0424 a601 ld a,#1
2672 0426 6b02 ld (OFST+0,sp),a
2674 0428 2041 jra L3231
2675 042a L7231:
2676 ; 813 pendingbitstatus = RESET;
2678 042a 0f02 clr (OFST+0,sp)
2679 042c 203d jra L3231
2680 042e L5231:
2681 ; 816 else if (UART2_IT == UART2_IT_LHDF)
2683 042e 1e03 ldw x,(OFST+1,sp)
2684 0430 a30412 cpw x,#1042
2685 0433 261c jrne L5331
2686 ; 819 enablestatus = (u8)((u8)UART2->CR6 & itmask2);
2688 0435 c65249 ld a,21065
2689 0438 1402 and a,(OFST+0,sp)
2690 043a 6b02 ld (OFST+0,sp),a
2691 ; 821 if (((UART2->CR6 & itpos) != (u8)0x00) && enablestatus)
2693 043c c65249 ld a,21065
2694 043f 1501 bcp a,(OFST-1,sp)
2695 0441 270a jreq L7331
2697 0443 0d02 tnz (OFST+0,sp)
2698 0445 2706 jreq L7331
2699 ; 824 pendingbitstatus = SET;
2701 0447 a601 ld a,#1
2702 0449 6b02 ld (OFST+0,sp),a
2704 044b 201e jra L3231
2705 044d L7331:
2706 ; 829 pendingbitstatus = RESET;
2708 044d 0f02 clr (OFST+0,sp)
2709 044f 201a jra L3231
2710 0451 L5331:
2711 ; 835 enablestatus = (u8)((u8)UART2->CR2 & itmask2);
2713 0451 c65245 ld a,21061
2714 0454 1402 and a,(OFST+0,sp)
2715 0456 6b02 ld (OFST+0,sp),a
2716 ; 837 if (((UART2->SR & itpos) != (u8)0x00) && enablestatus)
2718 0458 c65240 ld a,21056
2719 045b 1501 bcp a,(OFST-1,sp)
2720 045d 270a jreq L5431
2722 045f 0d02 tnz (OFST+0,sp)
2723 0461 2706 jreq L5431
2724 ; 840 pendingbitstatus = SET;
2726 0463 a601 ld a,#1
2727 0465 6b02 ld (OFST+0,sp),a
2729 0467 2002 jra L3231
2730 0469 L5431:
2731 ; 845 pendingbitstatus = RESET;
2733 0469 0f02 clr (OFST+0,sp)
2734 046b L3231:
2735 ; 849 return pendingbitstatus;
2737 046b 7b02 ld a,(OFST+0,sp)
2740 046d 5b04 addw sp,#4
2741 046f 81 ret
2777 ; 876 void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT)
2777 ; 877 {
2778 switch .text
2779 0470 _UART2_ClearITPendingBit:
2781 0470 89 pushw x
2782 00000000 OFST: set 0
2785 ; 878 assert_param(IS_UART2_CLEAR_IT_OK(UART2_IT));
2787 ; 881 if (UART2_IT == UART2_IT_RXNE)
2789 0471 a30255 cpw x,#597
2790 0474 2606 jrne L7631
2791 ; 883 UART2->SR = (u8)~(UART2_SR_RXNE);
2793 0476 35df5240 mov 21056,#223
2795 047a 2011 jra L1731
2796 047c L7631:
2797 ; 886 else if (UART2_IT == UART2_IT_LBDF)
2799 047c 1e01 ldw x,(OFST+1,sp)
2800 047e a30346 cpw x,#838
2801 0481 2606 jrne L3731
2802 ; 888 UART2->CR4 &= (u8)~(UART2_CR4_LBDF);
2804 0483 72195247 bres 21063,#4
2806 0487 2004 jra L1731
2807 0489 L3731:
2808 ; 893 UART2->CR6 &= (u8)(~UART2_CR6_LHDF);
2810 0489 72135249 bres 21065,#1
2811 048d L1731:
2812 ; 895 }
2815 048d 85 popw x
2816 048e 81 ret
2851 ; 898 void putChr(char a)
2851 ; 899 {
2852 switch .text
2853 048f _putChr:
2857 ; 900 UART2_SendData8(a);
2859 048f cd02da call _UART2_SendData8
2861 ; 901 }
2864 0492 81 ret
2899 ; 904 void putChrLine(char a)
2899 ; 905 {
2900 switch .text
2901 0493 _putChrLine:
2905 ; 906 putChr(a);
2907 0493 adfa call _putChr
2909 ; 907 putChr('\r');
2911 0495 a60d ld a,#13
2912 0497 adf6 call _putChr
2914 ; 908 putChr('\n');
2916 0499 a60a ld a,#10
2917 049b adf2 call _putChr
2919 ; 909 }
2922 049d 81 ret
2968 ; 913 void putStr(char* a)
2968 ; 914 {
2969 switch .text
2970 049e _putStr:
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