?? stm8s_adc1.ls
字號:
2049 02e5 6b01 ld (OFST+0,sp),a
2050 02e7 L777:
2051 ; 543 return ((FlagStatus)status);
2053 02e7 7b01 ld a,(OFST+0,sp)
2056 02e9 85 popw x
2057 02ea 81 ret
2208 ; 552 FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag)
2208 ; 553 {
2209 switch .text
2210 02eb _ADC1_GetFlagStatus:
2212 02eb 88 push a
2213 02ec 88 push a
2214 00000001 OFST: set 1
2217 ; 554 u8 flagstatus = 0;
2219 02ed 7b01 ld a,(OFST+0,sp)
2220 02ef 97 ld xl,a
2221 ; 555 u8 temp = 0;
2223 02f0 7b01 ld a,(OFST+0,sp)
2224 02f2 97 ld xl,a
2225 ; 558 assert_param(IS_ADC1_FLAG_OK(Flag));
2227 ; 560 if ((Flag & 0x0F) == 0x01)
2229 02f3 7b02 ld a,(OFST+1,sp)
2230 02f5 a40f and a,#15
2231 02f7 a101 cp a,#1
2232 02f9 2609 jrne L5601
2233 ; 563 flagstatus = (u8)(ADC1->CR3 & ADC1_CR3_OVR);
2235 02fb c65403 ld a,21507
2236 02fe a440 and a,#64
2237 0300 6b01 ld (OFST+0,sp),a
2239 0302 2045 jra L7601
2240 0304 L5601:
2241 ; 565 else if ((Flag & 0xF0) == 0x10)
2243 0304 7b02 ld a,(OFST+1,sp)
2244 0306 a4f0 and a,#240
2245 0308 a110 cp a,#16
2246 030a 2636 jrne L1701
2247 ; 568 temp = (u8)(Flag & 0x0F);
2249 030c 7b02 ld a,(OFST+1,sp)
2250 030e a40f and a,#15
2251 0310 6b01 ld (OFST+0,sp),a
2252 ; 569 if (temp < 8)
2254 0312 7b01 ld a,(OFST+0,sp)
2255 0314 a108 cp a,#8
2256 0316 2414 jruge L3701
2257 ; 571 flagstatus = (u8)(ADC1->AWSRL & (1 << temp));
2259 0318 7b01 ld a,(OFST+0,sp)
2260 031a 5f clrw x
2261 031b 97 ld xl,a
2262 031c a601 ld a,#1
2263 031e 5d tnzw x
2264 031f 2704 jreq L021
2265 0321 L221:
2266 0321 48 sll a
2267 0322 5a decw x
2268 0323 26fc jrne L221
2269 0325 L021:
2270 0325 c4540d and a,21517
2271 0328 6b01 ld (OFST+0,sp),a
2273 032a 201d jra L7601
2274 032c L3701:
2275 ; 575 flagstatus = (u8)(ADC1->AWSRH & (1 << (temp - 8)));
2277 032c 7b01 ld a,(OFST+0,sp)
2278 032e a008 sub a,#8
2279 0330 5f clrw x
2280 0331 97 ld xl,a
2281 0332 a601 ld a,#1
2282 0334 5d tnzw x
2283 0335 2704 jreq L421
2284 0337 L621:
2285 0337 48 sll a
2286 0338 5a decw x
2287 0339 26fc jrne L621
2288 033b L421:
2289 033b c4540c and a,21516
2290 033e 6b01 ld (OFST+0,sp),a
2291 0340 2007 jra L7601
2292 0342 L1701:
2293 ; 580 flagstatus = (u8)(ADC1->CSR & Flag);
2295 0342 c65400 ld a,21504
2296 0345 1402 and a,(OFST+1,sp)
2297 0347 6b01 ld (OFST+0,sp),a
2298 0349 L7601:
2299 ; 582 return ((FlagStatus)flagstatus);
2301 0349 7b01 ld a,(OFST+0,sp)
2304 034b 85 popw x
2305 034c 81 ret
2349 ; 592 void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag)
2349 ; 593 {
2350 switch .text
2351 034d _ADC1_ClearFlag:
2353 034d 88 push a
2354 034e 88 push a
2355 00000001 OFST: set 1
2358 ; 594 u8 temp = 0;
2360 034f 0f01 clr (OFST+0,sp)
2361 ; 597 assert_param(IS_ADC1_FLAG_OK(Flag));
2363 ; 599 if ((Flag & 0x0F) == 0x01)
2365 0351 a40f and a,#15
2366 0353 a101 cp a,#1
2367 0355 2606 jrne L3211
2368 ; 602 ADC1->CR3 &= (u8)(~ADC1_CR3_OVR);
2370 0357 721d5403 bres 21507,#6
2372 035b 204b jra L5211
2373 035d L3211:
2374 ; 604 else if ((Flag & 0xF0) == 0x10)
2376 035d 7b02 ld a,(OFST+1,sp)
2377 035f a4f0 and a,#240
2378 0361 a110 cp a,#16
2379 0363 263a jrne L7211
2380 ; 607 temp = (u8)(Flag & 0x0F);
2382 0365 7b02 ld a,(OFST+1,sp)
2383 0367 a40f and a,#15
2384 0369 6b01 ld (OFST+0,sp),a
2385 ; 608 if (temp < 8)
2387 036b 7b01 ld a,(OFST+0,sp)
2388 036d a108 cp a,#8
2389 036f 2416 jruge L1311
2390 ; 610 ADC1->AWSRL &= (u8)(~((u8)1 << temp));
2392 0371 7b01 ld a,(OFST+0,sp)
2393 0373 5f clrw x
2394 0374 97 ld xl,a
2395 0375 a601 ld a,#1
2396 0377 5d tnzw x
2397 0378 2704 jreq L231
2398 037a L431:
2399 037a 48 sll a
2400 037b 5a decw x
2401 037c 26fc jrne L431
2402 037e L231:
2403 037e 43 cpl a
2404 037f c4540d and a,21517
2405 0382 c7540d ld 21517,a
2407 0385 2021 jra L5211
2408 0387 L1311:
2409 ; 614 ADC1->AWSRH &= (u8)(~((u8)1 << (temp - 8)));
2411 0387 7b01 ld a,(OFST+0,sp)
2412 0389 a008 sub a,#8
2413 038b 5f clrw x
2414 038c 97 ld xl,a
2415 038d a601 ld a,#1
2416 038f 5d tnzw x
2417 0390 2704 jreq L631
2418 0392 L041:
2419 0392 48 sll a
2420 0393 5a decw x
2421 0394 26fc jrne L041
2422 0396 L631:
2423 0396 43 cpl a
2424 0397 c4540c and a,21516
2425 039a c7540c ld 21516,a
2426 039d 2009 jra L5211
2427 039f L7211:
2428 ; 619 ADC1->CSR &= (u8) (~Flag);
2430 039f 7b02 ld a,(OFST+1,sp)
2431 03a1 43 cpl a
2432 03a2 c45400 and a,21504
2433 03a5 c75400 ld 21504,a
2434 03a8 L5211:
2435 ; 621 }
2438 03a8 85 popw x
2439 03a9 81 ret
2494 ; 641 ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit)
2494 ; 642 {
2495 switch .text
2496 03aa _ADC1_GetITStatus:
2498 03aa 89 pushw x
2499 03ab 88 push a
2500 00000001 OFST: set 1
2503 ; 643 ITStatus itstatus = RESET;
2505 03ac 7b01 ld a,(OFST+0,sp)
2506 03ae 97 ld xl,a
2507 ; 644 u8 temp = 0;
2509 03af 7b01 ld a,(OFST+0,sp)
2510 03b1 97 ld xl,a
2511 ; 647 assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
2513 ; 649 if ((ITPendingBit & 0xF0) == 0x10)
2515 03b2 7b02 ld a,(OFST+1,sp)
2516 03b4 97 ld xl,a
2517 03b5 7b03 ld a,(OFST+2,sp)
2518 03b7 a4f0 and a,#240
2519 03b9 5f clrw x
2520 03ba 02 rlwa x,a
2521 03bb a30010 cpw x,#16
2522 03be 2636 jrne L5611
2523 ; 652 temp = (u8)(ITPendingBit & 0x0F);
2525 03c0 7b03 ld a,(OFST+2,sp)
2526 03c2 a40f and a,#15
2527 03c4 6b01 ld (OFST+0,sp),a
2528 ; 653 if (temp < 8)
2530 03c6 7b01 ld a,(OFST+0,sp)
2531 03c8 a108 cp a,#8
2532 03ca 2414 jruge L7611
2533 ; 655 itstatus = (u8)(ADC1->AWSRL & (u8)((u8)1 << temp));
2535 03cc 7b01 ld a,(OFST+0,sp)
2536 03ce 5f clrw x
2537 03cf 97 ld xl,a
2538 03d0 a601 ld a,#1
2539 03d2 5d tnzw x
2540 03d3 2704 jreq L441
2541 03d5 L641:
2542 03d5 48 sll a
2543 03d6 5a decw x
2544 03d7 26fc jrne L641
2545 03d9 L441:
2546 03d9 c4540d and a,21517
2547 03dc 6b01 ld (OFST+0,sp),a
2549 03de 201d jra L3711
2550 03e0 L7611:
2551 ; 659 itstatus = (u8)(ADC1->AWSRH & (u8)((u8)1 << (temp - 8)));
2553 03e0 7b01 ld a,(OFST+0,sp)
2554 03e2 a008 sub a,#8
2555 03e4 5f clrw x
2556 03e5 97 ld xl,a
2557 03e6 a601 ld a,#1
2558 03e8 5d tnzw x
2559 03e9 2704 jreq L051
2560 03eb L251:
2561 03eb 48 sll a
2562 03ec 5a decw x
2563 03ed 26fc jrne L251
2564 03ef L051:
2565 03ef c4540c and a,21516
2566 03f2 6b01 ld (OFST+0,sp),a
2567 03f4 2007 jra L3711
2568 03f6 L5611:
2569 ; 664 itstatus = (u8)(ADC1->CSR & ITPendingBit);
2571 03f6 c65400 ld a,21504
2572 03f9 1403 and a,(OFST+2,sp)
2573 03fb 6b01 ld (OFST+0,sp),a
2574 03fd L3711:
2575 ; 666 return ((ITStatus)itstatus);
2577 03fd 7b01 ld a,(OFST+0,sp)
2580 03ff 5b03 addw sp,#3
2581 0401 81 ret
2626 ; 688 void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit)
2626 ; 689 {
2627 switch .text
2628 0402 _ADC1_ClearITPendingBit:
2630 0402 89 pushw x
2631 0403 88 push a
2632 00000001 OFST: set 1
2635 ; 690 u8 temp = 0;
2637 0404 0f01 clr (OFST+0,sp)
2638 ; 693 assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
2640 ; 695 if ((ITPendingBit& 0xF0) == 0x10)
2642 0406 01 rrwa x,a
2643 0407 a4f0 and a,#240
2644 0409 5f clrw x
2645 040a 02 rlwa x,a
2646 040b a30010 cpw x,#16
2647 040e 263a jrne L7121
2648 ; 698 temp = (u8)(ITPendingBit & 0x0F);
2650 0410 7b03 ld a,(OFST+2,sp)
2651 0412 a40f and a,#15
2652 0414 6b01 ld (OFST+0,sp),a
2653 ; 699 if (temp < 8)
2655 0416 7b01 ld a,(OFST+0,sp)
2656 0418 a108 cp a,#8
2657 041a 2416 jruge L1221
2658 ; 701 ADC1->AWSRL &= (u8)(~((u8)1 << temp));
2660 041c 7b01 ld a,(OFST+0,sp)
2661 041e 5f clrw x
2662 041f 97 ld xl,a
2663 0420 a601 ld a,#1
2664 0422 5d tnzw x
2665 0423 2704 jreq L651
2666 0425 L061:
2667 0425 48 sll a
2668 0426 5a decw x
2669 0427 26fc jrne L061
2670 0429 L651:
2671 0429 43 cpl a
2672 042a c4540d and a,21517
2673 042d c7540d ld 21517,a
2675 0430 2021 jra L5221
2676 0432 L1221:
2677 ; 705 ADC1->AWSRH &= (u8)(~((u8)1 << (temp - 8)));
2679 0432 7b01 ld a,(OFST+0,sp)
2680 0434 a008 sub a,#8
2681 0436 5f clrw x
2682 0437 97 ld xl,a
2683 0438 a601 ld a,#1
2684 043a 5d tnzw x
2685 043b 2704 jreq L261
2686 043d L461:
2687 043d 48 sll a
2688 043e 5a decw x
2689 043f 26fc jrne L461
2690 0441 L261:
2691 0441 43 cpl a
2692 0442 c4540c and a,21516
2693 0445 c7540c ld 21516,a
2694 0448 2009 jra L5221
2695 044a L7121:
2696 ; 710 ADC1->CSR &= (u8) (~ITPendingBit);
2698 044a 7b03 ld a,(OFST+2,sp)
2699 044c 43 cpl a
2700 044d c45400 and a,21504
2701 0450 c75400 ld 21504,a
2702 0453 L5221:
2703 ; 712 }
2706 0453 5b03 addw sp,#3
2707 0455 81 ret
2720 xdef _ADC1_ClearITPendingBit
2721 xdef _ADC1_GetITStatus
2722 xdef _ADC1_ClearFlag
2723 xdef _ADC1_GetFlagStatus
2724 xdef _ADC1_GetAWDChannelStatus
2725 xdef _ADC1_GetBufferValue
2726 xdef _ADC1_SetLowThreshold
2727 xdef _ADC1_SetHighThreshold
2728 xdef _ADC1_GetConversionValue
2729 xdef _ADC1_StartConversion
2730 xdef _ADC1_AWDChannelConfig
2731 xdef _ADC1_ExternalTriggerConfig
2732 xdef _ADC1_ConversionConfig
2733 xdef _ADC1_SchmittTriggerConfig
2734 xdef _ADC1_PrescalerConfig
2735 xdef _ADC1_ITConfig
2736 xdef _ADC1_DataBufferCmd
2737 xdef _ADC1_ScanModeCmd
2738 xdef _ADC1_Cmd
2739 xdef _ADC1_Init
2740 xdef _ADC1_DeInit
2759 end
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