?? stm8s_tim3.ls
字號:
2016 0202 _TIM3_OC1PolarityConfig:
2020 ; 576 assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
2022 ; 579 if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
2024 0202 4d tnz a
2025 0203 2706 jreq L3601
2026 ; 581 TIM3->CCER1 |= TIM3_CCER1_CC1P;
2028 0205 72125327 bset 21287,#1
2030 0209 2004 jra L5601
2031 020b L3601:
2032 ; 585 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1P);
2034 020b 72135327 bres 21287,#1
2035 020f L5601:
2036 ; 587 }
2039 020f 81 ret
2075 ; 598 void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
2075 ; 599 {
2076 switch .text
2077 0210 _TIM3_OC2PolarityConfig:
2081 ; 601 assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
2083 ; 604 if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
2085 0210 4d tnz a
2086 0211 2706 jreq L5011
2087 ; 606 TIM3->CCER1 |= TIM3_CCER1_CC2P;
2089 0213 721a5327 bset 21287,#5
2091 0217 2004 jra L7011
2092 0219 L5011:
2093 ; 610 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2P);
2095 0219 721b5327 bres 21287,#5
2096 021d L7011:
2097 ; 612 }
2100 021d 81 ret
2145 ; 625 void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
2145 ; 626 {
2146 switch .text
2147 021e _TIM3_CCxCmd:
2149 021e 89 pushw x
2150 00000000 OFST: set 0
2153 ; 628 assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
2155 ; 629 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2157 ; 631 if (TIM3_Channel == TIM3_CHANNEL_1)
2159 021f 9e ld a,xh
2160 0220 4d tnz a
2161 0221 2610 jrne L3311
2162 ; 634 if (NewState != DISABLE)
2164 0223 9f ld a,xl
2165 0224 4d tnz a
2166 0225 2706 jreq L5311
2167 ; 636 TIM3->CCER1 |= TIM3_CCER1_CC1E;
2169 0227 72105327 bset 21287,#0
2171 022b 2014 jra L1411
2172 022d L5311:
2173 ; 640 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1E);
2175 022d 72115327 bres 21287,#0
2176 0231 200e jra L1411
2177 0233 L3311:
2178 ; 647 if (NewState != DISABLE)
2180 0233 0d02 tnz (OFST+2,sp)
2181 0235 2706 jreq L3411
2182 ; 649 TIM3->CCER1 |= TIM3_CCER1_CC2E;
2184 0237 72185327 bset 21287,#4
2186 023b 2004 jra L1411
2187 023d L3411:
2188 ; 653 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2E);
2190 023d 72195327 bres 21287,#4
2191 0241 L1411:
2192 ; 657 }
2195 0241 85 popw x
2196 0242 81 ret
2241 ; 678 void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel, TIM3_OCMode_TypeDef TIM3_OCMode)
2241 ; 679 {
2242 switch .text
2243 0243 _TIM3_SelectOCxM:
2245 0243 89 pushw x
2246 00000000 OFST: set 0
2249 ; 681 assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
2251 ; 682 assert_param(IS_TIM3_OCM_OK(TIM3_OCMode));
2253 ; 684 if (TIM3_Channel == TIM3_CHANNEL_1)
2255 0244 9e ld a,xh
2256 0245 4d tnz a
2257 0246 2610 jrne L1711
2258 ; 687 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1E);
2260 0248 72115327 bres 21287,#0
2261 ; 690 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_OCMode);
2263 024c c65325 ld a,21285
2264 024f a48f and a,#143
2265 0251 1a02 or a,(OFST+2,sp)
2266 0253 c75325 ld 21285,a
2268 0256 200e jra L3711
2269 0258 L1711:
2270 ; 695 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2E);
2272 0258 72195327 bres 21287,#4
2273 ; 698 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_OCMode);
2275 025c c65326 ld a,21286
2276 025f a48f and a,#143
2277 0261 1a02 or a,(OFST+2,sp)
2278 0263 c75326 ld 21286,a
2279 0266 L3711:
2280 ; 700 }
2283 0266 85 popw x
2284 0267 81 ret
2318 ; 709 void TIM3_SetCounter(u16 Counter)
2318 ; 710 {
2319 switch .text
2320 0268 _TIM3_SetCounter:
2324 ; 712 TIM3->CNTRH = (u8)(Counter >> 8);
2326 0268 9e ld a,xh
2327 0269 c75328 ld 21288,a
2328 ; 713 TIM3->CNTRL = (u8)(Counter);
2330 026c 9f ld a,xl
2331 026d c75329 ld 21289,a
2332 ; 715 }
2335 0270 81 ret
2369 ; 724 void TIM3_SetAutoreload(u16 Autoreload)
2369 ; 725 {
2370 switch .text
2371 0271 _TIM3_SetAutoreload:
2375 ; 727 TIM3->ARRH = (u8)(Autoreload >> 8);
2377 0271 9e ld a,xh
2378 0272 c7532b ld 21291,a
2379 ; 728 TIM3->ARRL = (u8)(Autoreload);
2381 0275 9f ld a,xl
2382 0276 c7532c ld 21292,a
2383 ; 729 }
2386 0279 81 ret
2420 ; 738 void TIM3_SetCompare1(u16 Compare1)
2420 ; 739 {
2421 switch .text
2422 027a _TIM3_SetCompare1:
2426 ; 741 TIM3->CCR1H = (u8)(Compare1 >> 8);
2428 027a 9e ld a,xh
2429 027b c7532d ld 21293,a
2430 ; 742 TIM3->CCR1L = (u8)(Compare1);
2432 027e 9f ld a,xl
2433 027f c7532e ld 21294,a
2434 ; 743 }
2437 0282 81 ret
2471 ; 752 void TIM3_SetCompare2(u16 Compare2)
2471 ; 753 {
2472 switch .text
2473 0283 _TIM3_SetCompare2:
2477 ; 755 TIM3->CCR2H = (u8)(Compare2 >> 8);
2479 0283 9e ld a,xh
2480 0284 c7532f ld 21295,a
2481 ; 756 TIM3->CCR2L = (u8)(Compare2);
2483 0287 9f ld a,xl
2484 0288 c75330 ld 21296,a
2485 ; 757 }
2488 028b 81 ret
2524 ; 770 void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler)
2524 ; 771 {
2525 switch .text
2526 028c _TIM3_SetIC1Prescaler:
2528 028c 88 push a
2529 00000000 OFST: set 0
2532 ; 773 assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC1Prescaler));
2534 ; 776 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~TIM3_CCMR_ICxPSC)) | (u8)TIM3_IC1Prescaler);
2536 028d c65325 ld a,21285
2537 0290 a4f3 and a,#243
2538 0292 1a01 or a,(OFST+1,sp)
2539 0294 c75325 ld 21285,a
2540 ; 777 }
2543 0297 84 pop a
2544 0298 81 ret
2580 ; 789 void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler)
2580 ; 790 {
2581 switch .text
2582 0299 _TIM3_SetIC2Prescaler:
2584 0299 88 push a
2585 00000000 OFST: set 0
2588 ; 792 assert_param(IS_TIM3_IC_PRESCALER_OK(TIM3_IC2Prescaler));
2590 ; 795 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~TIM3_CCMR_ICxPSC)) | (u8)TIM3_IC2Prescaler);
2592 029a c65326 ld a,21286
2593 029d a4f3 and a,#243
2594 029f 1a01 or a,(OFST+1,sp)
2595 02a1 c75326 ld 21286,a
2596 ; 796 }
2599 02a4 84 pop a
2600 02a5 81 ret
2652 ; 803 u16 TIM3_GetCapture1(void)
2652 ; 804 {
2653 switch .text
2654 02a6 _TIM3_GetCapture1:
2656 02a6 5204 subw sp,#4
2657 00000004 OFST: set 4
2660 ; 806 u16 tmpccr1 = 0;
2662 02a8 1e03 ldw x,(OFST-1,sp)
2663 ; 807 u8 tmpccr1l=0, tmpccr1h=0;
2665 02aa 7b01 ld a,(OFST-3,sp)
2666 02ac 97 ld xl,a
2669 02ad 7b02 ld a,(OFST-2,sp)
2670 02af 97 ld xl,a
2671 ; 809 tmpccr1h = TIM3->CCR1H;
2673 02b0 c6532d ld a,21293
2674 02b3 6b02 ld (OFST-2,sp),a
2675 ; 810 tmpccr1l = TIM3->CCR1L;
2677 02b5 c6532e ld a,21294
2678 02b8 6b01 ld (OFST-3,sp),a
2679 ; 812 tmpccr1 = (u16)(tmpccr1l);
2681 02ba 7b01 ld a,(OFST-3,sp)
2682 02bc 5f clrw x
2683 02bd 97 ld xl,a
2684 02be 1f03 ldw (OFST-1,sp),x
2685 ; 813 tmpccr1 |= (u16)((u16)tmpccr1h << 8);
2687 02c0 7b02 ld a,(OFST-2,sp)
2688 02c2 5f clrw x
2689 02c3 97 ld xl,a
2690 02c4 4f clr a
2691 02c5 02 rlwa x,a
2692 02c6 01 rrwa x,a
2693 02c7 1a04 or a,(OFST+0,sp)
2694 02c9 01 rrwa x,a
2695 02ca 1a03 or a,(OFST-1,sp)
2696 02cc 01 rrwa x,a
2697 02cd 1f03 ldw (OFST-1,sp),x
2698 ; 815 return (u16)tmpccr1;
2700 02cf 1e03 ldw x,(OFST-1,sp)
2703 02d1 5b04 addw sp,#4
2704 02d3 81 ret
2756 ; 824 u16 TIM3_GetCapture2(void)
2756 ; 825 {
2757 switch .text
2758 02d4 _TIM3_GetCapture2:
2760 02d4 5204 subw sp,#4
2761 00000004 OFST: set 4
2764 ; 827 u16 tmpccr2 = 0;
2766 02d6 1e03 ldw x,(OFST-1,sp)
2767 ; 828 u8 tmpccr2l=0, tmpccr2h=0;
2769 02d8 7b01 ld a,(OFST-3,sp)
2770 02da 97 ld xl,a
2773 02db 7b02 ld a,(OFST-2,sp)
2774 02dd 97 ld xl,a
2775 ; 830 tmpccr2h = TIM3->CCR2H;
2777 02de c6532f ld a,21295
2778 02e1 6b02 ld (OFST-2,sp),a
2779 ; 831 tmpccr2l = TIM3->CCR2L;
2781 02e3 c65330 ld a,21296
2782 02e6 6b01 ld (OFST-3,sp),a
2783 ; 833 tmpccr2 = (u16)(tmpccr2l);
2785 02e8 7b01 ld a,(OFST-3,sp)
2786 02ea 5f clrw x
2787 02eb 97 ld xl,a
2788 02ec 1f03 ldw (OFST-1,sp),x
2789 ; 834 tmpccr2 |= (u16)((u16)tmpccr2h << 8);
2791 02ee 7b02 ld a,(OFST-2,sp)
2792 02f0 5f clrw x
2793 02f1 97 ld xl,a
2794 02f2 4f clr a
2795 02f3 02 rlwa x,a
2796 02f4 01 rrwa x,a
2797 02f5 1a04 or a,(OFST+0,sp)
2798 02f7 01 rrwa x,a
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