Quartus II 32-bit
Version 11.1 Build 173 11/01/2011 SJ Full Version
49
4708
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
|megacore|turbo_codec-v1.2.0|lib|
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
lp_rx_top_cyclone
# storage
db|lp_rx_top_cyclone.(0).cnf
db|lp_rx_top_cyclone.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lp_rx_top_cyclone.v
afeac8ff15243780ddd177dd86b62e47
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
DEVICE
Cyclone
PARAMETER_STRING
DEF
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
lp_rx
# storage
db|lp_rx_top_cyclone.(1).cnf
db|lp_rx_top_cyclone.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|fpga_test|ts201_altera|link_port-v1.1.0|source|verilog|lp_rx.v
8c2e613828b5cabb68e014b0193a497
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
DEVICE
Cyclone
PARAMETER_STRING
USR
}
# hierarchies {
lp_rx:lp_rx
}
# macro_sequence

# end
# entity
dcfifo
# storage
db|lp_rx_top_cyclone.(2).cnf
db|lp_rx_top_cyclone.(2).cnf
# case_insensitive
# source_file
dcfifo.tdf
70b9603ae4a0d985f67137cfe328eec7
7
# user_parameter {
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
33
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
128
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
7
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
3
PARAMETER_UNKNOWN
DEF
WRSYNC_DELAYPIPE
3
PARAMETER_UNKNOWN
DEF
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
ADD_USEDW_MSB_BIT
OFF
PARAMETER_UNKNOWN
DEF
WRITE_ACLR_SYNCH
OFF
PARAMETER_UNKNOWN
DEF
READ_ACLR_SYNCH
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
dcfifo_1nm1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrusedw
-1
3
wrreq
-1
3
wrclk
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q
-1
3
data
-1
3
aclr
-1
3
}
# include_file {
altdpram.inc
2f9e6727b678ffd76e72bc5a95a2630
alt_sync_fifo.inc
a019bef5b1e7379dfab915daa2a6c4
a_graycounter.inc
c8eabdd6f8e7d384595a15fec505aa8
altsyncram_fifo.inc
4b2b21790828dd59a04a16f08af58b
a_gray2bin.inc
7e4b761bbeb1a382a47a2f89c3e13e
lpm_counter.inc
c5cfeeabc5f2ab60b3453f6abbc42b41
dffpipe.inc
5471cd80ee441dd293deca0963c9aa0
lpm_add_sub.inc
144a73b61081a2a03554ff5acc5e8842
a_fefifo.inc
5a44f50e786a1d286adceb22796b9f
aglobal111.inc
9cc1f9de5ad83fc94dd171c3f7986bd
lpm_compare.inc
bbd3e8c93afb7320934629e5fb11566
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo
}
# macro_sequence

# end
# entity
dcfifo_1nm1
# storage
db|lp_rx_top_cyclone.(3).cnf
db|lp_rx_top_cyclone.(3).cnf
# case_insensitive
# source_file
db|dcfifo_1nm1.tdf
ae8df2c5c03eaf641a6f877db9f8166
7
# used_port {
wrusedw6
-1
3
wrusedw5
-1
3
wrusedw4
-1
3
wrusedw3
-1
3
wrusedw2
-1
3
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrclk
-1
3
rdreq
-1
3
rdempty
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q32
-1
3
q31
-1
3
q30
-1
3
q3
-1
3
q29
-1
3
q28
-1
3
q27
-1
3
q26
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
aclr
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated
}
# macro_sequence

# end
# entity
a_fefifo_qec
# storage
db|lp_rx_top_cyclone.(4).cnf
db|lp_rx_top_cyclone.(4).cnf
# case_insensitive
# source_file
db|a_fefifo_qec.tdf
1565b71cde8196be23eb755142c3fb6c
7
# used_port {
usedw_in6
-1
3
usedw_in5
-1
3
usedw_in4
-1
3
usedw_in3
-1
3
usedw_in2
-1
3
usedw_in1
-1
3
usedw_in0
-1
3
rreq
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|a_fefifo_qec:read_state
}
# macro_sequence

# end
# entity
a_fefifo_3bc
# storage
db|lp_rx_top_cyclone.(5).cnf
db|lp_rx_top_cyclone.(5).cnf
# case_insensitive
# source_file
db|a_fefifo_3bc.tdf
9419c4e7f149b377c92846c6242bd49c
7
# used_port {
wreq
-1
3
usedw_in6
-1
3
usedw_in5
-1
3
usedw_in4
-1
3
usedw_in3
-1
3
usedw_in2
-1
3
usedw_in1
-1
3
usedw_in0
-1
3
full
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|a_fefifo_3bc:write_state
}
# macro_sequence

# end
# entity
a_gray2bin_o4b
# storage
db|lp_rx_top_cyclone.(6).cnf
db|lp_rx_top_cyclone.(6).cnf
# case_insensitive
# source_file
db|a_gray2bin_o4b.tdf
2caeeac8f0b357a959474b8bcf162c
7
# used_port {
gray6
-1
3
gray5
-1
3
gray4
-1
3
gray3
-1
3
gray2
-1
3
gray1
-1
3
gray0
-1
3
bin6
-1
3
bin5
-1
3
bin4
-1
3
bin3
-1
3
bin2
-1
3
bin1
-1
3
bin0
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|a_gray2bin_o4b:gray2bin_rs_nbwp
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|a_gray2bin_o4b:gray2bin_ws_nbrp
}
# macro_sequence

# end
# entity
a_graycounter_s06
# storage
db|lp_rx_top_cyclone.(7).cnf
db|lp_rx_top_cyclone.(7).cnf
# case_insensitive
# source_file
db|a_graycounter_s06.tdf
e24db563d5b6906a12a1db7a7d3f37cc
7
# used_port {
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|a_graycounter_s06:rdptr_g
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|a_graycounter_s06:wrptr_g
}
# macro_sequence

# end
# entity
dpram_t241
# storage
db|lp_rx_top_cyclone.(8).cnf
db|lp_rx_top_cyclone.(8).cnf
# case_insensitive
# source_file
db|dpram_t241.tdf
2eec5cf757dec6e9c795b65304d93c
7
# used_port {
wren
-1
3
wraddress6
-1
3
wraddress5
-1
3
wraddress4
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress6
-1
3
rdaddress5
-1
3
rdaddress4
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q32
-1
3
q31
-1
3
q30
-1
3
q3
-1
3
q29
-1
3
q28
-1
3
q27
-1
3
q26
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|dpram_t241:fiforam
}
# macro_sequence

# end
# entity
altsyncram_eqh1
# storage
db|lp_rx_top_cyclone.(9).cnf
db|lp_rx_top_cyclone.(9).cnf
# case_insensitive
# source_file
db|altsyncram_eqh1.tdf
25f30e34082f56812812e77a64929fa
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|dpram_t241:fiforam|altsyncram_eqh1:altsyncram6
}
# macro_sequence

# end
# entity
dffpipe_ed9
# storage
db|lp_rx_top_cyclone.(10).cnf
db|lp_rx_top_cyclone.(10).cnf
# case_insensitive
# source_file
db|dffpipe_ed9.tdf
235db4b4878bdaf5f8e9972f43919b96
7
# used_port {
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|dffpipe_ed9:dffpipe_rdbuw
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|dffpipe_ed9:dffpipe_rdusedw
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|dffpipe_ed9:dffpipe_rs_dbwp
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|dffpipe_ed9:dffpipe_wr_dbuw
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|dffpipe_ed9:dffpipe_wrusedw
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|dffpipe_ed9:dffpipe_ws_nbrp
}
# macro_sequence

# end
# entity
alt_synch_pipe_mc8
# storage
db|lp_rx_top_cyclone.(11).cnf
db|lp_rx_top_cyclone.(11).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_mc8.tdf
f62f43418f9a6489168113cac65737d
7
# used_port {
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|alt_synch_pipe_mc8:dffpipe_ws_dgrp
}
# macro_sequence

# end
# entity
dffpipe_gd9
# storage
db|lp_rx_top_cyclone.(12).cnf
db|lp_rx_top_cyclone.(12).cnf
# case_insensitive
# source_file
db|dffpipe_gd9.tdf
847651b78b14aeb81ab78dddfbdaadd3
7
# used_port {
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|alt_synch_pipe_mc8:dffpipe_rs_dgwp|dffpipe_gd9:dffpipe9
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|alt_synch_pipe_mc8:dffpipe_ws_dgrp|dffpipe_gd9:dffpipe9
}
# macro_sequence

# end
# entity
add_sub_eub
# storage
db|lp_rx_top_cyclone.(13).cnf
db|lp_rx_top_cyclone.(13).cnf
# case_insensitive
# source_file
db|add_sub_eub.tdf
46175cdf039e1b6126f59085822f
7
# used_port {
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|add_sub_eub:lpm_add_sub_rd_udwn
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|add_sub_eub:lpm_add_sub_wr_udwn
}
# macro_sequence

# end
# entity
cntr_ata
# storage
db|lp_rx_top_cyclone.(14).cnf
db|lp_rx_top_cyclone.(14).cnf
# case_insensitive
# source_file
db|cntr_ata.tdf
346a286e60c5565334cc74aaf6556a41
7
# used_port {
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|cntr_ata:rdptr_b
lp_rx:lp_rx|dcfifo:rx_fifo|dcfifo_1nm1:auto_generated|cntr_ata:wrptr_b
}
# macro_sequence

# end
# complete