# ================================================================================
# (c) 2003 Altera Corporation. All rights reserved.
# Altera products are protected under numerous U.S. and foreign patents, maskwork
# rights, copyrights and other intellectual property laws.
# 
# This reference design file, and your use thereof, is subject to and governed
# by the terms and conditions of the applicable Altera Reference Design License
# Agreement (either as signed by you, agreed by you upon download or as a
# "click-through" agreement upon installation andor found at www.altera.com).
# By using this reference design file, you indicate your acceptance of such terms
# and conditions between you and Altera Corporation.  In the event that you do
# not agree with such terms and conditions, you may not use the reference design
# file and please promptly destroy any copies you have made.
# 
# This reference design file is being provided on an "as-is" basis and as an
# accommodation and therefore all warranties, representations or guarantees of
# any kind (whether express, implied or statutory) including, without limitation,
# warranties of merchantability, non-infringement, or fitness for a particular
# purpose, are specifically disclaimed.  By making this reference design file
# available, Altera expressly does not recommend, suggest or require that this
# reference design file be used in combination with any other product not
# provided by Altera.
# ================================================================================

vlib work
vmap work work

vlog C:/quartus/eda/sim_lib/altera_mf.v
vlog -reportprogress 300 -work work rx_test_harness.v
vlog -reportprogress 300 -work work ../../../source/verilog/lp_rx.v

vsim work.rx_tb

view wave
do rx_wave.do

run -all