/////////////////////////////////////////////////////////////////////////                                                             ////////  USB function core                                          ////////                                                             ////////                                                             ////////  Author: Rudolf Usselmann                                   ////////          rudi@asics.ws                                      ////////                                                             ////////                                                             ////////  Downloaded from: http://www.opencores.org/cores/usb/       ////////                                                             /////////////////////////////////////////////////////////////////////////////                                                             //////// Copyright (C) 2000 Rudolf Usselmann                         ////////                    rudi@asics.ws                            ////////                                                             //////// This source file may be used and distributed without        //////// restriction provided that this copyright statement is not   //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer.////////                                                             ////////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     //////// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   //////// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   //////// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      //////// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         //////// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    //////// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   //////// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        //////// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  //////// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  //////// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  //////// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         //////// POSSIBILITY OF SUCH DAMAGE.                                 ////////                                                             ///////////////////////////////////////////////////////////////////////////  CVS Log////  $Id: usbf_top.v,v 1.2 2001/08/10 08:48:33 rudi Exp $////  $Date: 2001/08/10 08:48:33 $//  $Revision: 1.2 $//  $Author: rudi $//  $Locker:  $//  $State: Exp $//// Change History://               $Log: usbf_top.v,v $//               Revision 1.2  2001/08/10 08:48:33  rudi////               - Changed IO names to be more clear.//               - Uniquifyed define names to be core specific.////               Revision 1.1  2001/08/03 05:30:09  rudi//////               1) Reorganized directory structure////               Revision 1.2  2001/03/31 13:00:52  rudi////               - Added Core configuration//               - Added handling of OUT packets less than MAX_PL_SZ in DMA mode//               - Modified WISHBONE interface and sync logic//               - Moved SSRAM outside the core (added interface)//               - Many small bug fixes ...////               Revision 1.0  2001/03/07 09:17:12  rudi//////               Changed all revisions to revision 1.0. This is because OpenCores CVS//               interface could not handle the original '0.1' revision ....////               Revision 0.2  2001/03/07 09:08:13  rudi////               Added USB control signaling (Line Status) block. Fixed some minor//               typos, added resume bit and signal.////               Revision 0.1.0.1  2001/02/28 08:11:40  rudi//               Initial Release////`include "usbf_defines.v"module usbf_top(// WISHBONE Interface		clk_i, rst_i, wb_addr_i, wb_data_i, wb_data_o,		wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i, inta_o, intb_o,		dma_req_o, dma_ack_i, susp_o, resume_req_i,		// UTMI Interface		phy_clk_pad_i, phy_rst_pad_o,		DataOut_pad_o, TxValid_pad_o, TxReady_pad_i,		RxValid_pad_i, RxActive_pad_i, RxError_pad_i,		DataIn_pad_i, XcvSelect_pad_o, TermSel_pad_o,		SuspendM_pad_o, LineState_pad_i,		OpMode_pad_o, usb_vbus_pad_i,		VControl_Load_pad_o, VControl_pad_o, VStatus_pad_i,		// Buffer Memory Interface		sram_adr_o, sram_data_i, sram_data_o, sram_re_o, sram_we_o		);parameter	SSRAM_HADR = `USBF_SSRAM_HADR;input		clk_i;input		rst_i;input	[`USBF_UFC_HADR:0]	wb_addr_i;input	[31:0]	wb_data_i;output	[31:0]	wb_data_o;output		wb_ack_o;input		wb_we_i;input		wb_stb_i;input		wb_cyc_i;output		inta_o;output		intb_o;output	[15:0]	dma_req_o;input	[15:0]	dma_ack_i;output		susp_o;input		resume_req_i;input		phy_clk_pad_i;output		phy_rst_pad_o;output	[7:0]	DataOut_pad_o;output		TxValid_pad_o;input		TxReady_pad_i;input	[7:0]	DataIn_pad_i;input		RxValid_pad_i;input		RxActive_pad_i;input		RxError_pad_i;output		XcvSelect_pad_o;output		TermSel_pad_o;output		SuspendM_pad_o;input	[1:0]	LineState_pad_i;output	[1:0]	OpMode_pad_o;input		usb_vbus_pad_i;output		VControl_Load_pad_o;output	[3:0]	VControl_pad_o;input	[7:0]	VStatus_pad_i;output	[SSRAM_HADR:0]	sram_adr_o;input	[31:0]	sram_data_i;output	[31:0]	sram_data_o;output		sram_re_o;output		sram_we_o;/////////////////////////////////////////////////////////////////////// Local Wires and Registers//// UTMI Interfacewire	[7:0]	rx_data;wire		rx_valid, rx_active, rx_err;wire	[7:0]	tx_data;wire		tx_valid;wire		tx_ready;wire		tx_first;wire		tx_valid_last;// Misc UTMI USB statuswire		mode_hs;	// High Speed Modewire		usb_reset;	// USB Resetwire		usb_suspend;	// USB Sleepwire		usb_attached;	// Attached to USBwire		resume_req;	// Resume Request// Memory Arbiter Interfacewire	[SSRAM_HADR:0]	madr;		// word addresswire	[31:0]	mdout;wire	[31:0]	mdin;wire		mwe;wire		mreq;wire		mack;wire		rst;// Wishbone Memory interfacewire	[`USBF_UFC_HADR:0]	ma_adr;wire	[31:0]	ma2wb_d;wire	[31:0]	wb2ma_d;wire		ma_we;wire		ma_req;wire		ma_ack;// WISHBONE Register File interfacewire		rf_re;wire		rf_we;wire	[31:0]	wb2rf_d;wire	[31:0]	rf2wb_d;// Internal Register File Interfacewire	[6:0]	funct_adr;	// This functions address (set by controller)wire	[31:0]	idin;		// Data Inputwire	[3:0]	ep_sel;		// Endpoint Number Inputwire		match;		// Endpoint Matchedwire		dma_in_buf_sz1;wire		dma_out_buf_avail;wire		buf0_rl;	// Reload Buf 0 with original valueswire		buf0_set;	// Write to buf 0wire		buf1_set;	// Write to buf 1wire		uc_bsel_set;	// Write to the uc_bsel fieldwire		uc_dpd_set;	// Write to the uc_dpd fieldwire		int_buf1_set;	// Set buf1 full/empty interruptwire		int_buf0_set;	// Set buf0 full/empty interruptwire		int_upid_set;	// Set unsupported PID interruptwire		int_crc16_set;	// Set CRC16 error interruptwire		int_to_set;	// Set time out interruptwire		int_seqerr_set;	// Set PID sequence error interruptwire		out_to_small;	// OUT packet was to small for DMA operationwire	[31:0]	csr;		// Internal CSR Outputwire	[31:0]	buf0;		// Internal Buf 0 Outputwire	[31:0]	buf1;		// Internal Buf 1 Outputwire	[31:0]	frm_nat;	// Frame Number and Time Registerwire		nse_err;	// No Such Endpoint Errorwire		pid_cs_err;	// PID CS errorwire		crc5_err;	// CRC5 Errorwire		rf_resume_req;	// Resume Request From main CSRreg		susp_o;/////////////////////////////////////////////////////////////////////// Misc Logic//assign rst = rst_i;assign phy_rst_pad_o = ~rst;assign resume_req = resume_req_i;always @(posedge clk_i)	susp_o <= #1 usb_suspend;/////////////////////////////////////////////////////////////////////// Module Instantiations//// UTMI Interfaceusbf_utmi_if	u0(		.phy_clk(	phy_clk_pad_i	),		.rst(		rst		),		.DataOut(	DataOut_pad_o	),		.TxValid(	TxValid_pad_o	),		.TxReady(	TxReady_pad_i	),		.RxValid(	RxValid_pad_i	),		.RxActive(	RxActive_pad_i	),		.RxError(	RxError_pad_i	),		.DataIn(	DataIn_pad_i	),		.XcvSelect(	XcvSelect_pad_o	),		.TermSel(	TermSel_pad_o	),		.SuspendM(	SuspendM_pad_o	),		.LineState(	LineState_pad_i	),		.OpMode(	OpMode_pad_o	),		.usb_vbus(	usb_vbus_pad_i	),		.rx_data(	rx_data		),		.rx_valid(	rx_valid	),		.rx_active(	rx_active	),		.rx_err(	rx_err		),		.tx_data(	tx_data		),		.tx_valid(	tx_valid	),		.tx_valid_last(	tx_valid_last	),		.tx_ready(	tx_ready	),		.tx_first(	tx_first	),		.mode_hs(	mode_hs		),		.usb_reset(	usb_reset	),		.usb_suspend(	usb_suspend	),		.usb_attached(	usb_attached	),		.resume_req(	resume_req	)		);// Protocol Layerusbf_pl #(SSRAM_HADR)	u1(	.clk(			phy_clk_pad_i		),		.rst(			rst			),		.rx_data(		rx_data			),		.rx_valid(		rx_valid		),		.rx_active(		rx_active		),		.rx_err(		rx_err			),		.tx_data(		tx_data			),		.tx_valid(		tx_valid		),		.tx_valid_last(		tx_valid_last		),		.tx_ready(		tx_ready		),		.tx_first(		tx_first		),		.tx_valid_out(		TxValid_pad_o		),		.mode_hs(		mode_hs			),		.usb_reset(		usb_reset		),		.usb_suspend(		usb_suspend		),		.usb_attached(		usb_attached		),		.madr(			madr			),