; HI-TECH Software PICC Assembler header file.
; Definitions based on C header file: pic16f1946.h.

; NOTE: PICC assembler option -P is required to preprocess assembler sources. 

; Special Function Register definitions
INDF0		equ	0000h
INDF1		equ	0001h
PCL		equ	0002h
STATUS		equ	0003h
FSR0L		equ	0004h
FSR0H		equ	0005h
FSR1L		equ	0006h
FSR1H		equ	0007h
BSR		equ	0008h
WREG		equ	0009h
PCLATH		equ	000Ah
INTCON		equ	000Bh
PORTA		equ	000Ch
PORTB		equ	000Dh
PORTC		equ	000Eh
PORTD		equ	000Fh
PORTE		equ	0010h
PIR1		equ	0011h
PIR2		equ	0012h
PIR3		equ	0013h
PIR4		equ	0014h
TMR0		equ	0015h
TMR1L		equ	0016h
TMR1H		equ	0017h
T1CON		equ	0018h
T1GCON		equ	0019h
TMR2		equ	001Ah
PR2		equ	001Bh
T2CON		equ	001Ch
CPSCON0		equ	001Eh
CPSCON1		equ	001Fh
TRIS_REGA		equ	008Ch
TRIS_REGB		equ	008Dh
TRIS_REGC		equ	008Eh
TRIS_REGD		equ	008Fh
TRIS_REGE		equ	0090h
PIE1		equ	0091h
PIE2		equ	0092h
PIE3		equ	0093h
PIE4		equ	0094h
OPTION_REG_REG	equ	0095h
PCON		equ	0096h
WDTCON		equ	0097h
OSCTUNE		equ	0098h
OSCCON		equ	0099h
OSCSTAT		equ	009Ah
ADRESL		equ	009Bh
ADRESH		equ	009Ch
ADCON0		equ	009Dh
ADCON1		equ	009Eh
LATA		equ	010Ch
LATB		equ	010Dh
LATC		equ	010Eh
LATD		equ	010Fh
LATE		equ	0110h
CM1CON0		equ	0111h
CM1CON1		equ	0112h
CM2CON0		equ	0113h
CM2CON1		equ	0114h
CMOUT		equ	0115h
BORCON		equ	0116h
FVRCON		equ	0117h
DACCON0		equ	0118h
DACCON1		equ	0119h
SRCON0		equ	011Ah
SRCON1		equ	011Bh
APFCON		equ	011Dh
CM3CON0		equ	011Eh
CM3CON1		equ	011Fh
ANSELA		equ	018Ch
ANSELE		equ	0190h
EEADRL		equ	0191h
EEADRH		equ	0192h
EEDATL		equ	0193h
EEDATA		equ	0193h
EEDATH		equ	0194h
EECON1		equ	0195h
EECON2		equ	0196h
RC1REG		equ	0199h
RCREG		equ	0199h
TX1REG		equ	019Ah
TXREG		equ	019Ah
SP1BRGL		equ	019Bh
SPBRG		equ	019Bh
SPBRGL		equ	019Bh
SP1BRGH		equ	019Ch
SPBRGH		equ	019Ch
RC1STA		equ	019Dh
RCSTA		equ	019Dh
TX1STA		equ	019Eh
TXSTA		equ	019Eh
BAUD1CON	equ	019Fh
WPUB		equ	020Dh
SSP1BUF		equ	0211h
SSPBUF		equ	0211h
SSP1ADD		equ	0212h
SSPADD		equ	0212h
SSP1MSK		equ	0213h
SSPMSK		equ	0213h
SSP1STAT	equ	0214h
SSPSTAT		equ	0214h
SSP1CON1	equ	0215h
SSPCON		equ	0215h
SSPCON1		equ	0215h
SSP1CON2	equ	0216h
SSPCON2		equ	0216h
SSP1CON3	equ	0217h
SSPCON3		equ	0217h
SSP2BUF		equ	0219h
SSP2ADD		equ	021Ah
SSP2MSK		equ	021Bh
SSP2STAT	equ	021Ch
SSP2CON1	equ	021Dh
SSP2CON2	equ	021Eh
SSP2CON3	equ	021Fh
PORTF		equ	028Ch
PORTG		equ	028Dh
CCPR1L		equ	0291h
CCPR1H		equ	0292h
CCP1CON		equ	0293h
PWM1CON		equ	0294h
CCP1AS		equ	0295h
ECCP1AS		equ	0295h
PSTR1CON	equ	0296h
CCPR2L		equ	0298h
CCPR2H		equ	0299h
CCP2CON		equ	029Ah
PWM2CON		equ	029Bh
CCP2AS		equ	029Ch
ECCP2AS		equ	029Ch
PSTR2CON	equ	029Dh
CCPTMRS0	equ	029Eh
CCPTMRS1	equ	029Fh
TRIS_REGF		equ	030Ch
TRIS_REGG		equ	030Dh
CCPR3L		equ	0311h
CCPR3H		equ	0312h
CCP3CON		equ	0313h
PWM3CON		equ	0314h
CCP3AS		equ	0315h
ECCP3AS		equ	0315h
PSTR3CON	equ	0316h
CCPR4L		equ	0318h
CCPR4H		equ	0319h
CCP4CON		equ	031Ah
CCPR5L		equ	031Ch
CCPR5H		equ	031Dh
CCP5CON		equ	031Eh
LATF		equ	038Ch
LATG		equ	038Dh
IOCBP		equ	0394h
IOCBN		equ	0395h
IOCBF		equ	0396h
ANSELF		equ	040Ch
ANSELG		equ	040Dh
TMR4		equ	0415h
PR4		equ	0416h
T4CON		equ	0417h
TMR6		equ	041Ch
PR6		equ	041Dh
T6CON		equ	041Eh
WPUG		equ	048Dh
RC2REG		equ	0491h
TX2REG		equ	0492h
SP2BRGL		equ	0493h
SPBRG2		equ	0493h
SP2BRGH		equ	0494h
RC2STA		equ	0495h
TX2STA		equ	0496h
BAUD2CON	equ	0497h
LCDCON		equ	0791h
LCDPS		equ	0792h
LCDREF		equ	0793h
LCDCST		equ	0794h
LCDRL		equ	0795h
LCDSE0		equ	0798h
LCDSE1		equ	0799h
LCDSE2		equ	079Ah
LCDSE3		equ	079Bh
LCDSE4		equ	079Ch
LCDSE5		equ	079Dh
LCDDATA0	equ	07A0h
LCDDATA1	equ	07A1h
LCDDATA2	equ	07A2h
LCDDATA3	equ	07A3h
LCDDATA4	equ	07A4h
LCDDATA5	equ	07A5h
LCDDATA6	equ	07A6h
LCDDATA7	equ	07A7h
LCDDATA8	equ	07A8h
LCDDATA9	equ	07A9h
LCDDATA10	equ	07AAh
LCDDATA11	equ	07ABh
LCDDATA12	equ	07ACh
LCDDATA13	equ	07ADh
LCDDATA14	equ	07AEh
LCDDATA15	equ	07AFh
LCDDATA16	equ	07B0h
LCDDATA17	equ	07B1h
LCDDATA18	equ	07B2h
LCDDATA19	equ	07B3h
LCDDATA20	equ	07B4h
LCDDATA21	equ	07B5h
LCDDATA22	equ	07B6h
LCDDATA23	equ	07B7h
STATUS_SHAD	equ	0FE4h
WREG_SHAD	equ	0FE5h
BSR_SHAD	equ	0FE6h
PCLATH_SHAD	equ	0FE7h
FSR0L_SHAD	equ	0FE8h
FSR0H_SHAD	equ	0FE9h
FSR1L_SHAD	equ	0FEAh
FSR1H_SHAD	equ	0FEBh
STKPTR		equ	0FEDh
TOSL		equ	0FEEh
TOSH		equ	0FEFh

; Bit variables associates within SFRs
#define CARRY_bit	STATUS,0
#define DC_bit	STATUS,1
#define ZERO_bit	STATUS,2
#define nPD_bit	STATUS,3
#define nTO_bit	STATUS,4
#define BSR0_bit	BSR,0
#define BSR1_bit	BSR,1
#define BSR2_bit	BSR,2
#define BSR3_bit	BSR,3
#define BSR4_bit	BSR,4
#define IOCIF_bit	INTCON,0
#define INTF_bit	INTCON,1
#define TMR0IF_bit	INTCON,2
#define IOCIE_bit	INTCON,3
#define INTE_bit	INTCON,4
#define TMR0IE_bit	INTCON,5
#define PEIE_bit	INTCON,6
#define GIE_bit	INTCON,7
#define RA0_bit	PORTA,0
#define RA1_bit	PORTA,1
#define RA2_bit	PORTA,2
#define RA3_bit	PORTA,3
#define RA4_bit	PORTA,4
#define RA5_bit	PORTA,5
#define RA6_bit	PORTA,6
#define RA7_bit	PORTA,7
#define RB0_bit	PORTB,0
#define RB1_bit	PORTB,1
#define RB2_bit	PORTB,2
#define RB3_bit	PORTB,3
#define RB4_bit	PORTB,4
#define RB5_bit	PORTB,5
#define RB6_bit	PORTB,6
#define RB7_bit	PORTB,7
#define RC0_bit	PORTC,0
#define RC1_bit	PORTC,1
#define RC2_bit	PORTC,2
#define RC3_bit	PORTC,3
#define RC4_bit	PORTC,4
#define RC5_bit	PORTC,5
#define RC6_bit	PORTC,6
#define RC7_bit	PORTC,7
#define RD0_bit	PORTD,0
#define RD1_bit	PORTD,1
#define RD2_bit	PORTD,2
#define RD3_bit	PORTD,3
#define RD4_bit	PORTD,4
#define RD5_bit	PORTD,5
#define RD6_bit	PORTD,6
#define RD7_bit	PORTD,7
#define RE0_bit	PORTE,0
#define RE1_bit	PORTE,1
#define RE2_bit	PORTE,2
#define RE3_bit	PORTE,3
#define RE4_bit	PORTE,4
#define RE5_bit	PORTE,5
#define RE6_bit	PORTE,6
#define RE7_bit	PORTE,7
#define TMR1IF_bit	PIR1,0
#define TMR2IF_bit	PIR1,1
#define CCP1IF_bit	PIR1,2
#define SSPIF_bit	PIR1,3
#define TXIF_bit	PIR1,4
#define RCIF_bit	PIR1,5
#define ADIF_bit	PIR1,6
#define TMR1GIF_bit	PIR1,7
#define CCP2IF_bit	PIR2,0
#define C3IF_bit	PIR2,1
#define LCDIF_bit	PIR2,2
#define BCLIF_bit	PIR2,3
#define EEIF_bit	PIR2,4
#define C1IF_bit	PIR2,5
#define C2IF_bit	PIR2,6
#define OSFIF_bit	PIR2,7
#define TMR4IF_bit	PIR3,1
#define TMR6IF_bit	PIR3,3
#define CCP3IF_bit	PIR3,4
#define CCP4IF_bit	PIR3,5
#define CCP5IF_bit	PIR3,6
#define SSP2IF_bit	PIR4,0
#define BCL2IF_bit	PIR4,1
#define TX2IF_bit	PIR4,4
#define RC2IF_bit	PIR4,5
#define TMR1ON_bit	T1CON,0
#define nT1SYNC_bit	T1CON,2
#define T1OSCEN_bit	T1CON,3
#define T1CKPS0_bit	T1CON,4
#define T1CKPS1_bit	T1CON,5
#define TMR1CS0_bit	T1CON,6
#define TMR1CS1_bit	T1CON,7
#define T1GSS0_bit	T1GCON,0
#define T1GSS1_bit	T1GCON,1
#define T1GVAL_bit	T1GCON,2
#define T1GGO_bit	T1GCON,3
#define T1GSPM_bit	T1GCON,4
#define T1GTM_bit	T1GCON,5
#define T1GPOL_bit	T1GCON,6
#define TMR1GE_bit	T1GCON,7
#define T2CKPS0_bit	T2CON,0
#define T2CKPS1_bit	T2CON,1
#define TMR2ON_bit	T2CON,2
#define T2OUTPS0_bit	T2CON,3
#define T2OUTPS1_bit	T2CON,4
#define T2OUTPS2_bit	T2CON,5
#define T2OUTPS3_bit	T2CON,6
#define T0XCS_bit	CPSCON0,0
#define CPSOUT_bit	CPSCON0,1
#define CPSRNG0_bit	CPSCON0,2
#define CPSRNG1_bit	CPSCON0,3
#define CPSON_bit	CPSCON0,7
#define CPSCH0_bit	CPSCON1,0
#define CPSCH1_bit	CPSCON1,1
#define CPSCH2_bit	CPSCON1,2
#define CPSCH3_bit	CPSCON1,3
#define CPSCH4_bit	CPSCON1,4
#define TRIS_REGA0_bit	TRIS_REGA,0
#define TRIS_REGA1_bit	TRIS_REGA,1
#define TRIS_REGA2_bit	TRIS_REGA,2
#define TRIS_REGA3_bit	TRIS_REGA,3
#define TRIS_REGA4_bit	TRIS_REGA,4
#define TRIS_REGA5_bit	TRIS_REGA,5
#define TRIS_REGA6_bit	TRIS_REGA,6
#define TRIS_REGA7_bit	TRIS_REGA,7
#define TRIS_REGB0_bit	TRIS_REGB,0
#define TRIS_REGB1_bit	TRIS_REGB,1
#define TRIS_REGB2_bit	TRIS_REGB,2
#define TRIS_REGB3_bit	TRIS_REGB,3
#define TRIS_REGB4_bit	TRIS_REGB,4
#define TRIS_REGB5_bit	TRIS_REGB,5
#define TRIS_REGB6_bit	TRIS_REGB,6
#define TRIS_REGB7_bit	TRIS_REGB,7
#define TRIS_REGC0_bit	TRIS_REGC,0
#define TRIS_REGC1_bit	TRIS_REGC,1
#define TRIS_REGC2_bit	TRIS_REGC,2
#define TRIS_REGC3_bit	TRIS_REGC,3
#define TRIS_REGC4_bit	TRIS_REGC,4
#define TRIS_REGC5_bit	TRIS_REGC,5
#define TRIS_REGC6_bit	TRIS_REGC,6
#define TRIS_REGC7_bit	TRIS_REGC,7
#define TRIS_REGD0_bit	TRIS_REGD,0
#define TRIS_REGD1_bit	TRIS_REGD,1
#define TRIS_REGD2_bit	TRIS_REGD,2
#define TRIS_REGD3_bit	TRIS_REGD,3
#define TRIS_REGD4_bit	TRIS_REGD,4
#define TRIS_REGD5_bit	TRIS_REGD,5
#define TRIS_REGD6_bit	TRIS_REGD,6
#define TRIS_REGD7_bit	TRIS_REGD,7
#define TRIS_REGE0_bit	TRIS_REGE,0
#define TRIS_REGE1_bit	TRIS_REGE,1
#define TRIS_REGE2_bit	TRIS_REGE,2
#define TRIS_REGE3_bit	TRIS_REGE,3
#define TRIS_REGE4_bit	TRIS_REGE,4
#define TRIS_REGE5_bit	TRIS_REGE,5
#define TRIS_REGE6_bit	TRIS_REGE,6
#define TRIS_REGE7_bit	TRIS_REGE,7
#define TMR1IE_bit	PIE1,0
#define TMR2IE_bit	PIE1,1
#define CCP1IE_bit	PIE1,2
#define SSPIE_bit	PIE1,3
#define TXIE_bit	PIE1,4
#define RCIE_bit	PIE1,5
#define ADIE_bit	PIE1,6
#define TMR1GIE_bit	PIE1,7
#define CCP2IE_bit	PIE2,0
#define C3IE_bit	PIE2,1
#define LCDIE_bit	PIE2,2
#define BCLIE_bit	PIE2,3
#define EEIE_bit	PIE2,4
#define C1IE_bit	PIE2,5
#define C2IE_bit	PIE2,6
#define OSFIE_bit	PIE2,7
#define TMR4IE_bit	PIE3,1
#define TMR6IE_bit	PIE3,3
#define CCP3IE_bit	PIE3,4
#define CCP4IE_bit	PIE3,5
#define CCP5IE_bit	PIE3,6
#define SSP2IE_bit	PIE4,0
#define BCL2IE_bit	PIE4,1
#define TX2IE_bit	PIE4,4
#define RC2IE_bit	PIE4,5
#define PS0_bit	OPTION_REG_REG,0
#define PS1_bit	OPTION_REG_REG,1
#define PS2_bit	OPTION_REG_REG,2
#define PSA_bit	OPTION_REG_REG,3
#define T0SE_bit	OPTION_REG_REG,4
#define T0CS_bit	OPTION_REG_REG,5
#define INTEDG_bit	OPTION_REG_REG,6
#define nWPUEN_bit	OPTION_REG_REG,7
#define nBOR_bit	PCON,0
#define nPOR_bit	PCON,1
#define nRI_bit	PCON,2
#define nRMCLR_bit	PCON,3
#define STKUNF_bit	PCON,6
#define STKOVF_bit	PCON,7
#define SWDTEN_bit	WDTCON,0
#define WDTPS0_bit	WDTCON,1
#define WDTPS1_bit	WDTCON,2
#define WDTPS2_bit	WDTCON,3
#define WDTPS3_bit	WDTCON,4
#define WDTPS4_bit	WDTCON,5
#define TUN0_bit	OSCTUNE,0
#define TUN1_bit	OSCTUNE,1
#define TUN2_bit	OSCTUNE,2
#define TUN3_bit	OSCTUNE,3
#define TUN4_bit	OSCTUNE,4
#define TUN5_bit	OSCTUNE,5
#define SCS0_bit	OSCCON,0
#define SCS1_bit	OSCCON,1
#define IRCF0_bit	OSCCON,3
#define IRCF1_bit	OSCCON,4
#define IRCF2_bit	OSCCON,5
#define IRCF3_bit	OSCCON,6
#define SPLLEN_bit	OSCCON,7
#define HFIOFS_bit	OSCSTAT,0
#define LFIOFR_bit	OSCSTAT,1
#define MFIOFR_bit	OSCSTAT,2
#define HFIOFL_bit	OSCSTAT,3
#define HFIOFR_bit	OSCSTAT,4
#define OSTS_bit	OSCSTAT,5
#define PLLR_bit	OSCSTAT,6
#define T1OSCR_bit	OSCSTAT,7
#define ADON_bit	ADCON0,0
#define GO_nDONE_bit	ADCON0,1
#define CHS0_bit	ADCON0,2
#define CHS1_bit	ADCON0,3
#define CHS2_bit	ADCON0,4
#define CHS3_bit	ADCON0,5
#define CHS4_bit	ADCON0,6
#define ADGO_bit	ADCON0,1
#define ADPREF0_bit	ADCON1,0
#define ADPREF1_bit	ADCON1,1
#define ADNREF_bit	ADCON1,2
#define ADCS0_bit	ADCON1,4
#define ADCS1_bit	ADCON1,5
#define ADCS2_bit	ADCON1,6
#define ADFM_bit	ADCON1,7
#define LATA0_bit	LATA,0
#define LATA1_bit	LATA,1
#define LATA2_bit	LATA,2
#define LATA3_bit	LATA,3
#define LATA4_bit	LATA,4
#define LATA5_bit	LATA,5
#define LATA6_bit	LATA,6
#define LATA7_bit	LATA,7
#define LATB0_bit	LATB,0
#define LATB1_bit	LATB,1
#define LATB2_bit	LATB,2
#define LATB3_bit	LATB,3
#define LATB4_bit	LATB,4
#define LATB5_bit	LATB,5
#define LATB6_bit	LATB,6
#define LATB7_bit	LATB,7
#define LATC0_bit	LATC,0
#define LATC1_bit	LATC,1
#define LATC2_bit	LATC,2
#define LATC3_bit	LATC,3
#define LATC4_bit	LATC,4
#define LATC5_bit	LATC,5
#define LATC6_bit	LATC,6
#define LATC7_bit	LATC,7
#define LATD0_bit	LATD,0
#define LATD1_bit	LATD,1
#define LATD2_bit	LATD,2
#define LATD3_bit	LATD,3
#define LATD4_bit	LATD,4
#define LATD5_bit	LATD,5
#define LATD6_bit	LATD,6
#define LATD7_bit	LATD,7
#define LATE0_bit	LATE,0
#define LATE1_bit	LATE,1
#define LATE2_bit	LATE,2
#define LATE3_bit	LATE,3
#define LATE4_bit	LATE,4
#define LATE5_bit	LATE,5
#define LATE6_bit	LATE,6
#define LATE7_bit	LATE,7
#define C1SYNC_bit	CM1CON0,0
#define C1HYS_bit	CM1CON0,1
#define C1SP_bit	CM1CON0,2
#define C1POL_bit	CM1CON0,4
#define C1OE_bit	CM1CON0,5
#define C1OUT_bit	CM1CON0,6
#define C1ON_bit	CM1CON0,7
#define C1NCH0_bit	CM1CON1,0
#define C1NCH1_bit	CM1CON1,1
#define C1PCH0_bit	CM1CON1,4
#define C1PCH1_bit	CM1CON1,5
#define C1INTN_bit	CM1CON1,6
#define C1INTP_bit	CM1CON1,7
#define C2SYNC_bit	CM2CON0,0
#define C2HYS_bit	CM2CON0,1
#define C2SP_bit	CM2CON0,2
#define C2POL_bit	CM2CON0,4
#define C2OE_bit	CM2CON0,5
#define C2OUT_bit	CM2CON0,6
#define C2ON_bit	CM2CON0,7
#define C2NCH0_bit	CM2CON1,0
#define C2NCH1_bit	CM2CON1,1
#define C2PCH0_bit	CM2CON1,4
#define C2PCH1_bit	CM2CON1,5
#define C2INTN_bit	CM2CON1,6
#define C2INTP_bit	CM2CON1,7
#define MC1OUT_bit	CMOUT,0
#define MC2OUT_bit	CMOUT,1
#define MC3OUT_bit	CMOUT,2
#define BORRDY_bit	BORCON,0
#define SBOREN_bit	BORCON,7
#define ADFVR0_bit	FVRCON,0
#define ADFVR1_bit	FVRCON,1
#define CDAFVR0_bit	FVRCON,2
#define CDAFVR1_bit	FVRCON,3
#define TSRNG_bit	FVRCON,4
#define TSEN_bit	FVRCON,5
#define FVRRDY_bit	FVRCON,6