/************************************************************************//*									*//*	File:	 mcf5307.h						*//*	Date:	 23 December 97						*//*	Purpose: This file contains the CPU specific types and data	*//*		 structures for the MCF5307.  The register field	*//*		 definitions will set the accompanying bits in the	*//*		 control register.					*//*	Author:	 Michael Norman <ra6329@email.sps.mot.com>		*//*		 Hyung Chang	<ra7011@email.sps.mot.com>		*//*									*//************************************************************************/#ifndef MCF5307_H#define MCF5307_H/************************************************************************//*									*//*  Definitions of the basic data types.				*//*									*//************************************************************************/typedef unsigned char		BYTE;		/*  8 bits */typedef unsigned short int	WORD;		/* 16 bits */typedef unsigned long int	LONG;		/* 32 bits */typedef signed char		SBYTE;		/*  8 bits */typedef signed short int	SWORD;		/* 16 bits */typedef signed long int		SLONG;		/* 32 bits */typedef unsigned char		NATURAL8;	/*  8 bits */typedef unsigned short int	NATURAL16;	/* 16 bits */typedef unsigned long int	NATURAL32;	/* 32 bits */typedef signed char		INTEGER8;	/*  8 bits */typedef signed short int	INTEGER16;	/* 16 bits */typedef signed long int		INTEGER32;	/* 32 bits */typedef NATURAL32	ADDRESS;	/* 32 bits */typedef WORD		INSTRUCTION;	/* for ILLEGAL and brkpnts */#define ILLEGAL		0x4AFC		/* 68K illegal instruction *//************************************************************************//*									*//*  Definition of what the single exception stack frame looks like.	*//*									*//************************************************************************/typedef struct{	NATURAL16	form_vector;	NATURAL16	status_register;	NATURAL32	program_counter;} STACK_FRAME;#define SF_FORMAT(a)	((a->form_vector & 0xF000)>>12)	/* Format to Align Stack	*/#define SF_VECTOR(a)	((a->form_vector & 0x03FC)>>2)	/* Exception Type		*/#define SF_SR(a)	(a->status_register)		/* Status Register		*/#define SF_PC(a)	(a->program_counter)		/* Program Counter		*/#define SF_FS(a)	(((a->form_vector & 0x0C00)>>8) | (a->form_vector & 0x0003))							/* Fault Status Field		*//************************************************************************//*									*//*  Integer Unit User Mode Registers					*//*	(except the SR which contains the CCR)				*//*									*//************************************************************************/typedef struct{	/* Order IS VERY IMPORTANT -- MOVEM instruction */	NATURAL32	d0, d1, d2, d3, d4, d5, d6, d7;	  /* Data Registers	*/	/* offset	00  04  08  12  16  20  24  28 */	NATURAL32	a0, a1, a2, a3, a4, a5, a6, a7;	  /* Address Registers	*/	/* offset	32  36  40  44  48  52  56  60 */	NATURAL32	pc;				  /* Program Counter	*/	/* offset	64 */	NATURAL16	sr;				  /* Status Register	*/	/* offset	68 */} REGISTERS;#define MCF5307_SR_T	   (0x8000)	/* Trace Enable			*/#define MCF5307_SR_S	   (0x2000)	/* Supervisor/User State	*/#define MCF5307_SR_M	   (0x1000)	/* Master/Interrupt State	*/#define MCF5307_SR_IPM(a)  (((a)&0700)<<8) /* Interrupt Priority Mask	*/#define MCF5307_SR_P	   (0x0080)	/* Branch Prediction Forward	*/#define MCF5307_SR_X	   (0x0010)	/* Extend Condition Code	*/#define MCF5307_SR_N	   (0x0008)	/* Negative Condition Code	*/#define MCF5307_SR_Z	   (0x0004)	/* Zero Condition Code		*/#define MCF5307_SR_V	   (0x0002)	/* Overflow Condition Code	*/#define MCF5307_SR_C	   (0x0001)	/* Carry Condition Code		*//************************************************************************//*									*//*  MAC Unit User Mode Registers					*//*									*//************************************************************************/typedef struct{	NATURAL32	ACC;	/* Accumulator		*/	NATURAL16	MASK;	/* Mask Register	*/	NATURAL8	MACSR;	/* MAC Status Register	*/} MCF5307_MAC;#define MCF5307_MAC_MACSR_OMC	(0x80)#define MCF5307_MAC_MACSR_SUPER	(0x40)#define MCF5307_MAC_MACSR_N	(0x08)	/* Negative Condition Code	*/#define MCF5307_MAC_MACSR_Z	(0x04)	/* Zero Condition Code		*/#define MCF5307_MAC_MACSR_V	(0x02)	/* Overflow Condition Code	*/#define MCF5307_MAC_MACSR_C	(0x01)	/* Carry Condition Code		*//************************************************************************//*									*//*  Supervisor Mode Registers (SR is grouped with User because of CCR)	*//*									*//************************************************************************/typedef struct{								/*  Rc	*/	NATURAL32	CACR;	/*Cache Control Register	:: $002 */	NATURAL32	ACR0;	/* Access Control Register	:: $004 */	NATURAL32	ACR1;	/* Access Control Register 1	:: $005 */	NATURAL32	VBR;	/* Vector Base Register		:: $801 */	NATURAL32	RAMBAR;	/* SRAM Base Address Register	:: $c04	*/	NATURAL32	MBAR;	/* Module Base Address Register	:: $c0f	*/} MCF5307_SUPERVISOR;#define MCF5307_CACR_EC		(0x80000000)	/* Cache Enable 		    */#define MCF5307_CACR_ESB	(0x20000000)	/* Enable Store Buffer		    */#define MCF5307_CACR_DPI	(0x10000000)	/* Disable CPUSHL Invalidation 	    */#define MCF5307_CACR_HLCK	(0x08000000)	/* 1/2 Cache Lock Mode		    */#define MCF5307_CACR_CINVA	(0x01000000)	/* Cache Invalidate All 	    */#define MCF5307_CACR_DNFB	(0x00000400)	/* Default Noncacheable Fill Buffer */#define MCF5307_CACR_DCM_00	(0x00000000)	/* Cacheable, writethrough	    */#define MCF5307_CACR_DCM_01	(0x00000100)	/* Cacheable, copyback		    */#define MCF5307_CACR_DCM_10	(0x00000200)	/* Cache-Inhibited, precise	    */#define MCF5307_CACR_DCM_11	(0x00000300)	/* Cache-Inhibited, imprecise	    */#define MCF5307_CACR_DW		(0x00000020)	/* Default Write Protect	    */#define MCF5307_ACR_BASE(a)	((a)&0xFF000000)	/* Address Base		    */#define MCF5307_ACR_MASK(a)	(((a)&0xFF000000)>>8)	/* Address Mask		    */#define MCF5307_ACR_E		(0x00008000)	/* Enable			    */#define MCF5307_ACR_S_USER	(0x00000000)	/* User Mode Access		    */#define MCF5307_ACR_S_SUPER	(0x00002000)	/* Supervisor Mode Access	    */#define MCF5307_ACR_S_IGNORE	(0x00004000)	/* Ignore Mode Access		    */#define MCF5307_ACR_CM_00	(0x00000000)	/* Cacheable, writethrough	    */#define MCF5307_ACR_CM_01	(0x00000020)	/* Cacheable, copyback		    */#define MCF5307_ACR_CM_10	(0x00000040)	/* Cache-Inhibited, precise	    */#define MCF5307_ACR_CM_11	(0x00000060)	/* Cache-Inhibited, imprecise	    */#define MCF5307_ACR_WP		(0x00000004)	/* Write Protect		    */#define MCF5307_VBR_BASE(a)	((a)&0xFFF00000)	/* Vector Base Address	    */#define MCF5307_RAMBAR_BASE(a)	((a)&0xFFFFFE00)	/* Base Address		    */#define MCF5307_RAMBAR_WP	(0x00000100)	/* Write Protect		    */#define MCF5307_RAMBAR_AS_CPU	(0x00000020)	/* CPU Space/Interrupt acknowledge  */#define MCF5307_RAMBAR_AS_SC	(0x00000010)	/* Supervisor Code		    */#define MCF5307_RAMBAR_AS_SD	(0x00000008)	/* Supervisor Data		    */#define MCF5307_RAMBAR_AS_UC	(0x00000004)	/* User Code			    */#define MCF5307_RAMBAR_AS_UD	(0x00000002)	/* User Data			    */#define MCF5307_RAMBAR_V	(0x00000001)	/* Valid 			    */#define MCF5307_MBAR_BASE(a)	((a)&0xFFFFFC00)	/* Base Address		    */#define MCF5307_MBAR_WP		(0x00000200)	/* Write Protect		    */#define MCF5307_MBAR_SC		(0x00000010)	/* Mask Supervisor Code Space	    */#define MCF5307_MBAR_SD		(0x00000008)	/* Mask Supervisor Data Space	    */#define MCF5307_MBAR_UC		(0x00000004)	/* Mask User Code Space		    */#define MCF5307_MBAR_UD		(0x00000002)	/* Mask User Data Space		    */#define MCF5307_MBAR_V		(0x00000001)	/* Valid			    *//************************************************************************//*									*//*  System Integration Registers					*//*									*//************************************************************************/typedef volatile struct{	NATURAL8	RSR;		/* Reset Status Register		    */	NATURAL8	SYPCR;		/* System Protection Control Register	    */	NATURAL8	SWIVR;		/* Software Watchdog Interrupt Vector Reg   */	NATURAL8	SWSR;		/* Software Watchdog Service Register	    */	NATURAL16	PAR;		/* Pin Assignment Register		    */	NATURAL8	IRQPAR;		/* Interrupt Assignment Register	    */	NATURAL8	reserved0;	NATURAL8	PLLCR;		/* Phase Locked Loop Control Register	    */	NATURAL8	reserved1;	NATURAL16	reserved2;	NATURAL8	MPARK;		/* MBus Park Register			    */	NATURAL8	reserved3;	NATURAL16	reserved4;	NATURAL32	reserved5[12];	NATURAL32	IPR;		/* Interrupt Pending Register		    */	NATURAL32	IMR;		/* Internal Mask Register		    */	NATURAL8	reserved6[3];	NATURAL8	AVCR;		/* Auto Vector Control Register		    */	NATURAL8	ICR0;		/* Interrupt Control Register:  SWT	    */	NATURAL8	ICR1;		/* Interrupt Control Register:  Timer 1	    */	NATURAL8	ICR2;		/* Interrupt Control Register:  Timer 2	    */	NATURAL8	ICR3;		/* Interrupt Control Register:  MBus	    */	NATURAL8	ICR4;		/* Interrupt Control Register:  UART 1	    */	NATURAL8	ICR5;		/* Interrupt Control Register:  UART 2	    */	NATURAL8	ICR6;		/* Interrupt Control Register:  DMA 0	    */	NATURAL8	ICR7;		/* Interrupt Control Register:  DMA 1	    */	NATURAL8	ICR8;		/* Interrupt Control Register:  DMA 2	    */	NATURAL8	ICR9;		/* Interrupt Control Register:  DMA 3	    */	NATURAL8	ICR10;		/* Interrupt Control Register:  Reserved    */	NATURAL8	ICR11;		/* Interrupt Control Register:  Reserved    */} MCF5307_SIM;#define MCF5307_SIM_RSR_HRST		(0x80)	/* Hard or System Reset		    */#define MCF5307_SIM_RSR_SWTR		(0x20)	/* Software Watchdog Timer Reset    */#define MCF5307_SIM_SYPCR_SWE		(0x80)	/* Software Watchdog Enable	    */#define MCF5307_SIM_SYPCR_SWRI		(0x40)	/* SW Reset/Interrupt Select	    */#define MCF5307_SIM_SYPCR_SWT_2_9	(0x00)	/* SW Timeout: 2^9  / Sys Freq	    */#define MCF5307_SIM_SYPCR_SWT_2_11	(0x08)	/* SW Timeout: 2^11 / Sys Freq	    */#define MCF5307_SIM_SYPCR_SWT_2_13	(0x10)	/* SW Timeout: 2^13 / Sys Freq	    */#define MCF5307_SIM_SYPCR_SWT_2_15	(0x18)	/* SW Timeout: 2^15 / Sys Freq	    */#define MCF5307_SIM_SYPCR_SWT_2_18	(0x20)	/* SW Timeout: 2^18 / Sys Freq	    */#define MCF5307_SIM_SYPCR_SWT_2_20	(0x28)	/* SW Timeout: 2^20 / Sys Freq	    */#define MCF5307_SIM_SYPCR_SWT_2_22	(0x30)	/* SW Timeout: 2^22 / Sys Freq	    */#define MCF5307_SIM_SYPCR_SWT_2_24	(0x38)	/* SW Timeout: 2^24 / Sys Freq	    */#define MCF5307_SIM_SYPCR_SWTA		(0x04)	/* SW Transfer Acknowledge Enable   */#define MCF5307_SIM_SYPCR_SWTAVAL	(0x02)	/* SW Transfer Acknowledge Valid    */#define MCF5307_SIM_SWSR_55		(0x55)		/* Write $55 to SWSR	    */#define MCF5307_SIM_SWSR_AA		(0xaa)		/* Write $AA to SWSR	    */#define MCF5307_SIM_PAR_ADDR31		(0x8000)	/* Assign Pin as ADDR31	    */#define MCF5307_SIM_PAR_ADDR30		(0x4000)	/* Assign Pin as ADDR30	    */#define MCF5307_SIM_PAR_ADDR29		(0x2000)	/* Assign Pin as ADDR29	    */#define MCF5307_SIM_PAR_ADDR28		(0x1000)	/* Assign Pin as ADDR28	    */#define MCF5307_SIM_PAR_ADDR27		(0x0800)	/* Assign Pin as ADDR27	    */#define MCF5307_SIM_PAR_ADDR26		(0x0400)	/* Assign Pin as ADDR26	    */#define MCF5307_SIM_PAR_ADDR25		(0x0200)	/* Assign Pin as ADDR25	    */#define MCF5307_SIM_PAR_ADDR24		(0x0100)	/* Assign Pin as ADDR24	    */#define MCF5307_SIM_PAR_XTIP		(0x0080)	/* Assign Pin as XTIP	    */#define MCF5307_SIM_PAR_DREQ0		(0x0040)	/* Assign Pin as DREQ0	    */#define MCF5307_SIM_PAR_DREQ1		(0x0020)	/* Assign Pin as DREQ1	    */#define MCF5307_SIM_PAR_TM2		(0x0010)	/* Assign Pin as TM2	    */#define MCF5307_SIM_PAR_TM1		(0x0008)	/* Assign Pin as TM1	    */#define MCF5307_SIM_PAR_TM0		(0x0004)	/* Assign Pin as TM0	    */#define MCF5307_SIM_PAR_TT1		(0x0002)	/* Assign Pin as TT1	    */#define MCF5307_SIM_PAR_TT0		(0x0001)	/* Assign Pin as TT0	    */#define MCF5307_SIM_IRQPAR_2		(0x80)	/* IRQ[5] pin to Int IL 4, not 5    */#define MCF5307_SIM_IRQPAR_1		(0x20)	/* IRQ[3] pin to Int IL 6, not 3    */#define MCF5307_SIM_IRQPAR_0		(0x10)	/* IRQ[1] pin to Int IL 2, not 1    */#define MCF5307_SIM_PLLCR_ENBSTOP	(0x80)	/* Enable CPU STOP Instruction	    */#define MCF5307_SIM_PLLCR_PLLIPL(a)	(((a)&0x07)<<4)	/* PLL Wake-up IPL	    */#define MCF5307_SIM_MPARK_PARK(a)	(((a)&0x03)<<6)	/* Default Bus Master	    */#define MCF5307_SIM_MPARK_E2MCTRL	(0x20)		/* EBus to MBus Arbitration */#define MCF5307_SIM_MPARK_EARBCTRL	(0x10)		/* SBus to EBus Arbitration */#define MCF5307_SIM_MPARK_SHOWDATA	(0x08)		/* Show SBus on EBus	    */#define MCF5307_SIM_IPR_DMA3		(0x00020000)	/* Interrupt Pending DMA3   */#define MCF5307_SIM_IPR_DMA2		(0x00010000)	/* Interrupt Pending DMA2   */#define MCF5307_SIM_IPR_DMA1		(0x00008000)	/* Interrupt Pending DMA1   */#define MCF5307_SIM_IPR_DMA0		(0x00004000)	/* Interrupt Pending DMA0   */