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/**MITSUBISHI**MITSUBISHI**MITSUBISHI**MITSUBISHI**MITSUBISHI**MITSUBISHI**/
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/*                                                                        */
/*       Internal register addresses for the M3061                        */
/*                                                                        */
/*       Name:        SFR_3061.H                                          */
/*       Date  :      04.04.1997                                          */
/*       Author:      ST                                                  */
/*       Change:                                                          */
/*               (Date)  (Author)  (Description)                          */
/*                                                                        */
/**************************************************************************/

/************************  Processor Registers  ***************************/

#define PM0    (*(unsigned char* ) 0x004)   // Processor Mode Register 0
#define PM1    (*(unsigned char* ) 0x005)   // Processor Mode Register 1
#define CM0    (*(unsigned char* ) 0x006)   // System clock control register 0 
#define CM1    (*(unsigned char* ) 0x007)   // System clock control register 1 
#define CM     (*(unsigned int * ) 0x006)   // System clock control register   
#define CSR    (*(unsigned char* ) 0x008)   // Chip select control register    

/************************  Watchdog Timer  ********************************/

#define WDTS   (*(unsigned char* ) 0x00E)   // Watchdog timer start register   
#define WDC    (*(unsigned char* ) 0x00F)   // Watchdog timer control register 

/************************  Interrupt Control Register  ********************/

#define AIER   (*(unsigned char* ) 0x009)   // Address match interrupt enable           
#define PRCR   (*(unsigned char* ) 0x00A)   // Protect register                         
#define RMAD00 (*(unsigned char* ) 0x010)   // Address match interrupt register 0 (low) 
#define RMAD01 (*(unsigned char* ) 0x011)   // Address match interrupt register 0 (mid) 
#define RMAD02 (*(unsigned char* ) 0x012)   // Address match interrupt register 0 (high)
#define RMAD10 (*(unsigned char* ) 0x014)   // Address match interrupt register 1 (low) 
#define RMAD11 (*(unsigned char* ) 0x015)   // Address match interrupt register 1 (mid) 
#define RMAD12 (*(unsigned char* ) 0x016)   // Address match interrupt register 1 (high)
#define DMA0IC (*(unsigned char* ) 0x04B)   // DMA0 interrupt control register          
#define DMA1IC (*(unsigned char* ) 0x04C)   // DMA1 interrupt control register          
#define KUPIC  (*(unsigned char* ) 0x04D)   // Key input interrupt control register
#define ADIC   (*(unsigned char* ) 0x04E)   // A-D converter interrupt control register
#define S0TIC  (*(unsigned char* ) 0x051)   // UART0 transmit interrupt control register
#define S0RIC  (*(unsigned char* ) 0x052)   // UART0 receive interrupt control register 
#define S1TIC  (*(unsigned char* ) 0x053)   // UART1 transmit interrupt control register
#define S1RIC  (*(unsigned char* ) 0x054)   // UART1 receive interrupt control register 
#define TA0IC  (*(unsigned char* ) 0x055)   // Timer A0 interrupt control register      
#define TA1IC  (*(unsigned char* ) 0x056)   // Timer A1 interrupt control register      
#define TA2IC  (*(unsigned char* ) 0x057)   // Timer A2 interrupt control register      
#define TA3IC  (*(unsigned char* ) 0x058)   // Timer A3 interrupt control register      
#define TA4IC  (*(unsigned char* ) 0x059)   // Timer A4 interrupt control register      
#define TB0IC  (*(unsigned char* ) 0x05A)   // Timer B0 interrupt control register      
#define TB1IC  (*(unsigned char* ) 0x05B)   // Timer B1 interrupt control register      
#define TB2IC  (*(unsigned char* ) 0x05C)   // Timer B2 interrupt control register      
#define INT0IC (*(unsigned char* ) 0x05D)   // Interrupt 0 interrupt control register   
#define INT1IC (*(unsigned char* ) 0x05E)   // Interrupt 1 interrupt control register   
#define INT2IC (*(unsigned char* ) 0x05F)   // Interrupt 2 interrupt control register   

/************************  DMA Registers  *********************************/

#define SAR00  (*(unsigned char**) 0x020)   // DMA0 source pointer (low)        
#define SAR01  (*(unsigned char**) 0x021)   // DMA0 source pointer (mid)        
#define SAR02  (*(unsigned char**) 0x022)   // DMA0 source pointer (high)       
#define DAR00  (*(unsigned char**) 0x024)   // DMA0 destination pointer (low)   
#define DAR01  (*(unsigned char**) 0x025)   // DMA0 destination pointer (mid)   
#define DAR02  (*(unsigned char**) 0x026)   // DMA0 destination pointer (high)  
#define TCR00  (*(unsigned char* ) 0x028)   // DMA0 transfer counter (low)      
#define TCR01  (*(unsigned char* ) 0x029)   // DMA0 transfer counter (high)     
#define TCR0   (*(unsigned int * ) 0x028)   // DMA0 transfer counter            
#define DM0CON (*(unsigned char* ) 0x02C)   // DMA0 control register            
								  
#define SAR10  (*(unsigned char**) 0x030)   // DMA1 source pointer (low)        
#define SAR11  (*(unsigned char**) 0x031)   // DMA1 source pointer (mid)        
#define SAR12  (*(unsigned char**) 0x032)   // DMA1 source pointer (high)       
#define DAR10  (*(unsigned char**) 0x034)   // DMA1 destination pointer (low)   
#define DAR11  (*(unsigned char**) 0x035)   // DMA1 destination pointer (mid)   
#define DAR12  (*(unsigned char**) 0x036)   // DMA1 destination pointer (high)  
#define TCR10  (*(unsigned char* ) 0x038)   // DMA1 transfer counter (low)      
#define TCR11  (*(unsigned char* ) 0x039)   // DMA1 transfer counter (high)     
#define TCR1   (*(unsigned int * ) 0x038)   // DMA1 transfer counter            
#define DM1CON (*(unsigned char* ) 0x03C)   // DMA1 control register            
								  
#define DM0SL  (*(unsigned char* )  0x3B8)   // DMA0 cause selection  
#define DM1SL  (*(unsigned char* )  0x3BA)   // DMA1 cause selection  

/************************  Timer Registers  *******************************/

#define TABSR  (*(unsigned char* ) 0x380)   // Timer A/B count start flags   
#define CPSRF  (*(unsigned char* ) 0x381)   // Clock prescaler reset flag    
#define ONSF   (*(unsigned char* ) 0x382)   // One-shot start flagl          
#define TRGSR  (*(unsigned char* ) 0x383)   // Trigger select register       
#define UDF    (*(unsigned char* ) 0x384)   // Up- down-count selection flag 
								  
#define TA0L   (*(unsigned char* ) 0x386)   // Timer A0 (low byte)  
#define TA0H   (*(unsigned char* ) 0x387)   // Timer A0 (high byte) 
#define TA0    (*(unsigned int * ) 0x386)   // Timer A0             
#define TA1L   (*(unsigned char* ) 0x388)   // Timer A1 (low byte)  
#define TA1H   (*(unsigned char* ) 0x389)   // Timer A1 (high byte) 
#define TA1    (*(unsigned int * ) 0x388)   // Timer A1             
#define TA2L   (*(unsigned char* ) 0x38A)   // Timer A2 (low byte)  
#define TA2H   (*(unsigned char* ) 0x38B)   // Timer A2 (high byte) 
#define TA2    (*(unsigned int * ) 0x38A)   // Timer A2             
#define TA3L   (*(unsigned char* ) 0x38C)   // Timer A3 (low byte)  
#define TA3H   (*(unsigned char* ) 0x38D)   // Timer A3 (high byte) 
#define TA3    (*(unsigned int * ) 0x38C)   // Timer A3             
#define TA4L   (*(unsigned char* ) 0x38E)   // Timer A4 (low byte)  
#define TA4H   (*(unsigned char* ) 0x38F)   // Timer A4 (high byte) 
#define TA4    (*(unsigned int * ) 0x38E)   // Timer A4