?? pidb_fuzzy.mdl
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Model {
Name "pidb_fuzzy"
Version 4.00
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
BlockNameDataTip off
BlockParametersDataTip on
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Fri Feb 11 09:39:12 2000"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Sun Aug 19 14:22:22 2001"
ModelVersionFormat "1.%<AutoIncrement:72>"
ConfigurationManager "none"
SimParamPage "Solver"
StartTime "0.0"
StopTime "19.0"
SolverMode "Auto"
Solver "ode4"
RelTol "1e-4"
AbsTol "auto"
Refine "1"
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "0.01"
MaxOrder 5
OutputOption "RefineOutputTimes"
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
LimitDataPoints off
MaxDataPoints "1000"
Decimation "1"
AlgebraicLoopMsg "warning"
MinStepSizeMsg "warning"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
InheritedTsInSrcMsg "warning"
SingleTaskRateTransMsg "none"
MultiTaskRateTransMsg "error"
IntegerOverflowMsg "warning"
CheckForMatrixSingularity "none"
UnnecessaryDatatypeConvMsg "none"
Int32ToFloatConvMsg "warning"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
LinearizationMsg "none"
VectorMatrixConversionMsg "none"
SfunCompatibilityCheckMsg "none"
BlockPriorityViolationMsg "warning"
ArrayBoundsChecking "none"
ConsistencyChecking "none"
ZeroCross on
Profile off
SimulationMode "normal"
RTWSystemTargetFile "grt.tlc"
RTWInlineParameters off
RTWRetainRTWFile off
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
TLCProfiler off
TLCDebug off
TLCCoverage off
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "oneshot"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect off
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
OptimizeBlockIOStorage on
BufferReuse on
ParameterPooling on
BlockReductionOpt off
RTWExpressionDepthLimit 5
BooleanDataType off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "pidb_fuzzy"
Location [222, 74, 767, 427]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Abs
Name "Abs"
Position [150, 155, 180, 185]
SaturateOnIntegerOverflow on
}
Block {
BlockType Clock
Name "Clock"
Position [20, 15, 40, 35]
DisplayTime off
Decimation "10"
}
Block {
BlockType Constant
Name "Constant"
Position [25, 185, 55, 215]
Value "7"
VectorParams1D on
}
Block {
BlockType Constant
Name "Constant1"
Position [25, 235, 55, 265]
Value "9.9"
VectorParams1D on
}
Block {
BlockType Display
Name "Display"
Ports [1]
Position [340, 205, 430, 235]
Format "short"
Decimation "1"
Floating off
SampleTime "-1"
}
Block {
BlockType Display
Name "Display1"
Ports [1]
Position [165, 280, 255, 310]
Format "short"
Decimation "1"
Floating off
SampleTime "-1"
}
Block {
BlockType Reference
Name "Fuzzy Logic \nController"
Ports [1, 1]
Position [225, 50, 285, 100]
FontName "Arial"
SourceBlock "fuzblock/Fuzzy Logic \nController"
SourceType "FIS"
fis "tippa"
}
Block {
BlockType Gain
Name "Gain"
Position [195, 157, 250, 183]
Gain "1000"
Multiplication "Element-wise(K.*u)"
SaturateOnIntegerOverflow on
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [410, 60, 440, 90]
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "1"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [160, 207, 190, 238]
Operator "AND"
Inputs "2"
}
Block {
BlockType Mux
Name "Mux"
Ports [2, 1]
Position [485, 21, 490, 59]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Mux
Name "Mux1"
Ports [4, 1]
Position [200, 50, 210, 100]
ShowName off
Inputs "4"
DisplayOption "bar"
}
Block {
BlockType SubSystem
Name "PID signals"
Ports [1, 3]
Position [120, 61, 165, 99]
ShowPortLabels on
TreatAsAtomicUnit off
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
System {
Name "PID signals"
Location [373, 113, 625, 278]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [25, 33, 55, 47]
Port "1"
LatchInput off
Interpolate on
}
Block {
BlockType Derivative
Name "Derivative"
Position [105, 100, 135, 130]
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [105, 50, 135, 80]
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Outport
Name "Out1"
Position [185, 33, 215, 47]
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Outport
Name "Out2"
Position [185, 68, 215, 82]
Port "2"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Outport
Name "Out3"
Position [185, 108, 215, 122]
Port "3"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Line {
SrcBlock "In1"
SrcPort 1
Points [15, 0]
Branch {
Points [0, 25]
Branch {
Points [0, 50]
DstBlock "Derivative"
DstPort 1
}
Branch {
Points [0, 0]
DstBlock "Integrator"
DstPort 1
}
}
Branch {
DstBlock "Out1"
DstPort 1
}
}
Line {
SrcBlock "Derivative"
SrcPort 1
DstBlock "Out3"
DstPort 1
}
Line {
SrcBlock "Integrator"
SrcPort 1
Points [30, 0]
DstBlock "Out2"
DstPort 1
}
}
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [235, 204, 265, 231]
Inputs "2"
Multiplication "Element-wise(.*)"
SaturateOnIntegerOverflow on
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator"
Position [95, 177, 125, 208]
Operator ">="
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator1"
Position [95, 242, 125, 273]
Operator ">="
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [505, 24, 535, 56]
Floating off
Location [6, 53, 209, 211]
Open on
NumInputPorts "1"
TickLabels "OneTimeTick"
ZoomMode "on"
List {
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