{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 09:39:42 2006 " "Info: Processing started: Sat Jul 15 09:39:42 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd" {  } {  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "lcd.v(114) " "Warning: (10268) Verilog HDL information at lcd.v(114): Always Construct contains both blocking and non-blocking assignments" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 114 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd " "Info: Elaborating entity \"lcd\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ison lcd.v(20) " "Info: (10035) Verilog HDL or VHDL information at lcd.v(20): object \"ison\" declared but not used" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_IGNORE_INIT" "lcd.v(61) " "Warning: Verilog HDL unsupported feature warning at lcd.v(61): Initial Construct is not supported and will be ignored" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 61 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 lcd.v(107) " "Warning: Verilog HDL assignment warning at lcd.v(107): truncated value with size 32 to match size of target (3)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 107 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(109) " "Warning: Verilog HDL assignment warning at lcd.v(109): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(111) " "Warning: Verilog HDL assignment warning at lcd.v(111): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 111 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(118) " "Warning: Verilog HDL assignment warning at lcd.v(118): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(119) " "Warning: Verilog HDL assignment warning at lcd.v(119): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 119 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(122) " "Warning: Verilog HDL assignment warning at lcd.v(122): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 122 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(123) " "Warning: Verilog HDL assignment warning at lcd.v(123): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(125) " "Warning: Verilog HDL assignment warning at lcd.v(125): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 125 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(126) " "Warning: Verilog HDL assignment warning at lcd.v(126): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 126 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(131) " "Warning: Verilog HDL assignment warning at lcd.v(131): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 131 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(132) " "Warning: Verilog HDL assignment warning at lcd.v(132): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 132 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(134) " "Warning: Verilog HDL assignment warning at lcd.v(134): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(135) " "Warning: Verilog HDL assignment warning at lcd.v(135): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 135 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(140) " "Warning: Verilog HDL assignment warning at lcd.v(140): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(141) " "Warning: Verilog HDL assignment warning at lcd.v(141): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 lcd.v(143) " "Warning: Verilog HDL assignment warning at lcd.v(143): truncated value with size 32 to match size of target (4)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(152) " "Warning: Verilog HDL assignment warning at lcd.v(152): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 152 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(153) " "Warning: Verilog HDL assignment warning at lcd.v(153): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 153 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(154) " "Warning: Verilog HDL assignment warning at lcd.v(154): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 154 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(155) " "Warning: Verilog HDL assignment warning at lcd.v(155): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 155 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(161) " "Warning: Verilog HDL assignment warning at lcd.v(161): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 161 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(162) " "Warning: Verilog HDL assignment warning at lcd.v(162): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 162 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(163) " "Warning: Verilog HDL assignment warning at lcd.v(163): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 163 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(168) " "Warning: Verilog HDL assignment warning at lcd.v(168): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 168 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(169) " "Warning: Verilog HDL assignment warning at lcd.v(169): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 169 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(174) " "Warning: Verilog HDL assignment warning at lcd.v(174): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 174 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(175) " "Warning: Verilog HDL assignment warning at lcd.v(175): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 175 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(186) " "Warning: Verilog HDL assignment warning at lcd.v(186): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 186 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 lcd.v(194) " "Warning: Verilog HDL assignment warning at lcd.v(194): truncated value with size 32 to match size of target (8)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 194 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(199) " "Warning: Verilog HDL assignment warning at lcd.v(199): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 199 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(205) " "Warning: Verilog HDL assignment warning at lcd.v(205): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 205 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(206) " "Warning: Verilog HDL assignment warning at lcd.v(206): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 206 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(207) " "Warning: Verilog HDL assignment warning at lcd.v(207): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 207 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(208) " "Warning: Verilog HDL assignment warning at lcd.v(208): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 208 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(214) " "Warning: Verilog HDL assignment warning at lcd.v(214): truncated value with size 32 to match size of target (7)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 214 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(215) " "Warning: Verilog HDL assignment warning at lcd.v(215): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 215 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(216) " "Warning: Verilog HDL assignment warning at lcd.v(216): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 216 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(221) " "Warning: Verilog HDL assignment warning at lcd.v(221): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 221 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(222) " "Warning: Verilog HDL assignment warning at lcd.v(222): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 222 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(227) " "Warning: Verilog HDL assignment warning at lcd.v(227): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 227 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(228) " "Warning: Verilog HDL assignment warning at lcd.v(228): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 228 0 0 } }  } 0}