?? lcd.map.qmsg
字號(hào):
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(239) " "Warning: Verilog HDL assignment warning at lcd.v(239): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 239 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 lcd.v(247) " "Warning: Verilog HDL assignment warning at lcd.v(247): truncated value with size 32 to match size of target (8)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 247 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(252) " "Warning: Verilog HDL assignment warning at lcd.v(252): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 252 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(258) " "Warning: Verilog HDL assignment warning at lcd.v(258): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 258 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(259) " "Warning: Verilog HDL assignment warning at lcd.v(259): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 259 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(260) " "Warning: Verilog HDL assignment warning at lcd.v(260): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 260 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(261) " "Warning: Verilog HDL assignment warning at lcd.v(261): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 261 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(262) " "Warning: Verilog HDL assignment warning at lcd.v(262): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 262 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(267) " "Warning: Verilog HDL assignment warning at lcd.v(267): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 267 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(268) " "Warning: Verilog HDL assignment warning at lcd.v(268): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 268 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(273) " "Warning: Verilog HDL assignment warning at lcd.v(273): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 273 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(274) " "Warning: Verilog HDL assignment warning at lcd.v(274): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 274 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(280) " "Warning: Verilog HDL assignment warning at lcd.v(280): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 280 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(305) " "Warning: Verilog HDL assignment warning at lcd.v(305): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 305 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(306) " "Warning: Verilog HDL assignment warning at lcd.v(306): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 306 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(307) " "Warning: Verilog HDL assignment warning at lcd.v(307): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 307 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(312) " "Warning: Verilog HDL assignment warning at lcd.v(312): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 312 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(313) " "Warning: Verilog HDL assignment warning at lcd.v(313): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 313 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(319) " "Warning: Verilog HDL assignment warning at lcd.v(319): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 319 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(346) " "Warning: Verilog HDL assignment warning at lcd.v(346): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 346 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(347) " "Warning: Verilog HDL assignment warning at lcd.v(347): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 347 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(348) " "Warning: Verilog HDL assignment warning at lcd.v(348): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 348 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(349) " "Warning: Verilog HDL assignment warning at lcd.v(349): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 349 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(350) " "Warning: Verilog HDL assignment warning at lcd.v(350): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 350 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(355) " "Warning: Verilog HDL assignment warning at lcd.v(355): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 355 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(356) " "Warning: Verilog HDL assignment warning at lcd.v(356): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 356 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(359) " "Warning: Verilog HDL assignment warning at lcd.v(359): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 359 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(362) " "Warning: Verilog HDL assignment warning at lcd.v(362): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 362 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(363) " "Warning: Verilog HDL assignment warning at lcd.v(363): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 363 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(364) " "Warning: Verilog HDL assignment warning at lcd.v(364): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 364 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(370) " "Warning: Verilog HDL assignment warning at lcd.v(370): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 370 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(395) " "Warning: Verilog HDL assignment warning at lcd.v(395): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 395 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(396) " "Warning: Verilog HDL assignment warning at lcd.v(396): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 396 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(397) " "Warning: Verilog HDL assignment warning at lcd.v(397): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 397 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(402) " "Warning: Verilog HDL assignment warning at lcd.v(402): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 402 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(403) " "Warning: Verilog HDL assignment warning at lcd.v(403): truncated value with size 32 to match size of target (1)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 403 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 lcd.v(409) " "Warning: Verilog HDL assignment warning at lcd.v(409): truncated value with size 32 to match size of target (7)" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 409 0 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[0\]\[6\] data_in GND " "Warning: Reduced register \"rom1\[0\]\[6\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[0\]\[5\] data_in GND " "Warning: Reduced register \"rom1\[0\]\[5\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[0\]\[4\] data_in GND " "Warning: Reduced register \"rom1\[0\]\[4\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "rom1\[0\]\[3\] High " "Info: Power-up level of register \"rom1\[0\]\[3\]\" is not specified -- using power-up level of High to minimize register" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[0\]\[3\] data_in VCC " "Warning: Reduced register \"rom1\[0\]\[3\]\" with stuck data_in port to stuck value VCC" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[0\]\[2\] data_in GND " "Warning: Reduced register \"rom1\[0\]\[2\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[0\]\[1\] data_in GND " "Warning: Reduced register \"rom1\[0\]\[1\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[0\]\[0\] data_in GND " "Warning: Reduced register \"rom1\[0\]\[0\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[1\]\[7\] data_in GND " "Warning: Reduced register \"rom1\[1\]\[7\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[1\]\[6\] data_in GND " "Warning: Reduced register \"rom1\[1\]\[6\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[1\]\[5\] data_in GND " "Warning: Reduced register \"rom1\[1\]\[5\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rom1\[1\]\[4\] data_in GND " "Warning: Reduced register \"rom1\[1\]\[4\]\" with stuck data_in port to stuck value GND" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 10 -1 0 } } } 0}
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