?? lcd.tan.qmsg
字號:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 2 -1 0 } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "en~reg0 " "Info: Detected ripple clock \"en~reg0\" as buffer" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 112 -1 0 } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en~reg0" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register addr\[3\] register data\[4\]~reg0 71.94 MHz 13.9 ns Internal " "Info: Clock \"clk\" has Internal fmax of 71.94 MHz between source register \"addr\[3\]\" and destination register \"data\[4\]~reg0\" (period= 13.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.800 ns + Longest register register " "Info: + Longest register to register delay is 12.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addr\[3\] 1 REG LC1_C27 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C27; Fanout = 32; REG Node = 'addr\[3\]'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "" { addr[3] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.400 ns) 2.600 ns data~4449 2 COMB LC1_C31 3 " "Info: 2: + IC(1.200 ns) + CELL(1.400 ns) = 2.600 ns; Loc. = LC1_C31; Fanout = 3; COMB Node = 'data~4449'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "2.600 ns" { addr[3] data~4449 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.700 ns) 7.200 ns data~4565 3 COMB LC7_A7 1 " "Info: 3: + IC(2.900 ns) + CELL(1.700 ns) = 7.200 ns; Loc. = LC7_A7; Fanout = 1; COMB Node = 'data~4565'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "4.600 ns" { data~4449 data~4565 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.700 ns) 11.700 ns data~4465 4 COMB LC6_B32 1 " "Info: 4: + IC(2.800 ns) + CELL(1.700 ns) = 11.700 ns; Loc. = LC6_B32; Fanout = 1; COMB Node = 'data~4465'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "4.500 ns" { data~4565 data~4465 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 12.800 ns data\[4\]~reg0 5 REG LC1_B32 2 " "Info: 5: + IC(0.300 ns) + CELL(0.800 ns) = 12.800 ns; Loc. = LC1_B32; Fanout = 2; REG Node = 'data\[4\]~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "1.100 ns" { data~4465 data[4]~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.600 ns 43.75 % " "Info: Total cell delay = 5.600 ns ( 43.75 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns 56.25 % " "Info: Total interconnect delay = 7.200 ns ( 56.25 % )" { } { } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "12.800 ns" { addr[3] data~4449 data~4565 data~4465 data[4]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.800 ns" { addr[3] data~4449 data~4565 data~4465 data[4]~reg0 } { 0.000ns 1.200ns 2.900ns 2.800ns 0.300ns } { 0.000ns 1.400ns 1.700ns 1.700ns 0.800ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 4; CLK Node = 'clk'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns en~reg0 2 REG LC1_A2 56 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_A2; Fanout = 56; REG Node = 'en~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "0.900 ns" { clk en~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 112 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 5.500 ns data\[4\]~reg0 3 REG LC1_B32 2 " "Info: 3: + IC(2.600 ns) + CELL(0.000 ns) = 5.500 ns; Loc. = LC1_B32; Fanout = 2; REG Node = 'data\[4\]~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "2.600 ns" { en~reg0 data[4]~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 45.45 % " "Info: Total cell delay = 2.500 ns ( 45.45 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 54.55 % " "Info: Total interconnect delay = 3.000 ns ( 54.55 % )" { } { } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 data[4]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 data[4]~reg0 } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 4; CLK Node = 'clk'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns en~reg0 2 REG LC1_A2 56 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_A2; Fanout = 56; REG Node = 'en~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "0.900 ns" { clk en~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 112 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 5.500 ns addr\[3\] 3 REG LC1_C27 32 " "Info: 3: + IC(2.600 ns) + CELL(0.000 ns) = 5.500 ns; Loc. = LC1_C27; Fanout = 32; REG Node = 'addr\[3\]'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "2.600 ns" { en~reg0 addr[3] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 19 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 45.45 % " "Info: Total cell delay = 2.500 ns ( 45.45 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 54.55 % " "Info: Total interconnect delay = 3.000 ns ( 54.55 % )" { } { } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 addr[3] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 addr[3] } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 data[4]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 data[4]~reg0 } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 addr[3] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 addr[3] } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 19 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } } } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "12.800 ns" { addr[3] data~4449 data~4565 data~4465 data[4]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.800 ns" { addr[3] data~4449 data~4565 data~4465 data[4]~reg0 } { 0.000ns 1.200ns 2.900ns 2.800ns 0.300ns } { 0.000ns 1.400ns 1.700ns 1.700ns 0.800ns } } } { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 data[4]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 data[4]~reg0 } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 addr[3] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 addr[3] } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "data\[4\]~reg0 rst clk 9.400 ns register " "Info: tsu for register \"data\[4\]~reg0\" (data pin = \"rst\", clock pin = \"clk\") is 9.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.300 ns + Longest pin register " "Info: + Longest pin to register delay is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns rst 1 PIN PIN_56 99 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 99; PIN Node = 'rst'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "" { rst } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.600 ns) 4.100 ns data~4449 2 COMB LC1_C31 3 " "Info: 2: + IC(0.500 ns) + CELL(1.600 ns) = 4.100 ns; Loc. = LC1_C31; Fanout = 3; COMB Node = 'data~4449'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "2.100 ns" { rst data~4449 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.700 ns) 8.700 ns data~4565 3 COMB LC7_A7 1 " "Info: 3: + IC(2.900 ns) + CELL(1.700 ns) = 8.700 ns; Loc. = LC7_A7; Fanout = 1; COMB Node = 'data~4565'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "4.600 ns" { data~4449 data~4565 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.700 ns) 13.200 ns data~4465 4 COMB LC6_B32 1 " "Info: 4: + IC(2.800 ns) + CELL(1.700 ns) = 13.200 ns; Loc. = LC6_B32; Fanout = 1; COMB Node = 'data~4465'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "4.500 ns" { data~4565 data~4465 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 14.300 ns data\[4\]~reg0 5 REG LC1_B32 2 " "Info: 5: + IC(0.300 ns) + CELL(0.800 ns) = 14.300 ns; Loc. = LC1_B32; Fanout = 2; REG Node = 'data\[4\]~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "1.100 ns" { data~4465 data[4]~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.800 ns 54.55 % " "Info: Total cell delay = 7.800 ns ( 54.55 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.500 ns 45.45 % " "Info: Total interconnect delay = 6.500 ns ( 45.45 % )" { } { } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "14.300 ns" { rst data~4449 data~4565 data~4465 data[4]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "14.300 ns" { rst rst~out data~4449 data~4565 data~4465 data[4]~reg0 } { 0.000ns 0.000ns 0.500ns 2.900ns 2.800ns 0.300ns } { 0.000ns 2.000ns 1.600ns 1.700ns 1.700ns 0.800ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 4; CLK Node = 'clk'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns en~reg0 2 REG LC1_A2 56 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_A2; Fanout = 56; REG Node = 'en~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "0.900 ns" { clk en~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 112 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 5.500 ns data\[4\]~reg0 3 REG LC1_B32 2 " "Info: 3: + IC(2.600 ns) + CELL(0.000 ns) = 5.500 ns; Loc. = LC1_B32; Fanout = 2; REG Node = 'data\[4\]~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "2.600 ns" { en~reg0 data[4]~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 45.45 % " "Info: Total cell delay = 2.500 ns ( 45.45 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 54.55 % " "Info: Total interconnect delay = 3.000 ns ( 54.55 % )" { } { } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 data[4]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 data[4]~reg0 } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "14.300 ns" { rst data~4449 data~4565 data~4465 data[4]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "14.300 ns" { rst rst~out data~4449 data~4565 data~4465 data[4]~reg0 } { 0.000ns 0.000ns 0.500ns 2.900ns 2.800ns 0.300ns } { 0.000ns 2.000ns 1.600ns 1.700ns 1.700ns 0.800ns } } } { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 data[4]~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 data[4]~reg0 } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk rs rs~reg0 14.500 ns register " "Info: tco from clock \"clk\" to destination pin \"rs\" through register \"rs~reg0\" is 14.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 4; CLK Node = 'clk'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns en~reg0 2 REG LC1_A2 56 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_A2; Fanout = 56; REG Node = 'en~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "0.900 ns" { clk en~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 112 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 5.500 ns rs~reg0 3 REG LC6_A35 3 " "Info: 3: + IC(2.600 ns) + CELL(0.000 ns) = 5.500 ns; Loc. = LC6_A35; Fanout = 3; REG Node = 'rs~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "2.600 ns" { en~reg0 rs~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 45.45 % " "Info: Total cell delay = 2.500 ns ( 45.45 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 54.55 % " "Info: Total interconnect delay = 3.000 ns ( 54.55 % )" { } { } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 rs~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 rs~reg0 } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns + Longest register pin " "Info: + Longest register to pin delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs~reg0 1 REG LC6_A35 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A35; Fanout = 3; REG Node = 'rs~reg0'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "" { rs~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(6.300 ns) 8.500 ns rs 2 PIN PIN_101 0 " "Info: 2: + IC(2.200 ns) + CELL(6.300 ns) = 8.500 ns; Loc. = PIN_101; Fanout = 0; PIN Node = 'rs'" { } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "8.500 ns" { rs~reg0 rs } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 74.12 % " "Info: Total cell delay = 6.300 ns ( 74.12 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 25.88 % " "Info: Total interconnect delay = 2.200 ns ( 25.88 % )" { } { } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "8.500 ns" { rs~reg0 rs } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.500 ns" { rs~reg0 rs } { 0.000ns 2.200ns } { 0.000ns 6.300ns } } } } 0} } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 rs~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 rs~reg0 } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "8.500 ns" { rs~reg0 rs } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "8.500 ns" { rs~reg0 rs } { 0.000ns 2.200ns } { 0.000ns 6.300ns } } } } 0}
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