{ "Info" "ITDB_TH_RESULT" "cs2~reg0 rst clk 3.700 ns register " "Info: th for register \"cs2~reg0\" (data pin = \"rst\", clock pin = \"clk\") is 3.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 4; CLK Node = 'clk'" {  } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns en~reg0 2 REG LC1_A2 56 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_A2; Fanout = 56; REG Node = 'en~reg0'" {  } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "0.900 ns" { clk en~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 112 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 5.500 ns cs2~reg0 3 REG LC5_A3 10 " "Info: 3: + IC(2.600 ns) + CELL(0.000 ns) = 5.500 ns; Loc. = LC5_A3; Fanout = 10; REG Node = 'cs2~reg0'" {  } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "2.600 ns" { en~reg0 cs2~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 45.45 % " "Info: Total cell delay = 2.500 ns ( 45.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 54.55 % " "Info: Total interconnect delay = 3.000 ns ( 54.55 % )" {  } {  } 0}  } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 cs2~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 cs2~reg0 } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns rst 1 PIN PIN_56 99 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 99; PIN Node = 'rst'" {  } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "" { rst } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 3.100 ns cs2~reg0 2 REG LC5_A3 10 " "Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 3.100 ns; Loc. = LC5_A3; Fanout = 10; REG Node = 'cs2~reg0'" {  } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "1.100 ns" { rst cs2~reg0 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.v" 436 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 96.77 % " "Info: Total cell delay = 3.000 ns ( 96.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns 3.23 % " "Info: Total interconnect delay = 0.100 ns ( 3.23 % )" {  } {  } 0}  } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "3.100 ns" { rst cs2~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "3.100 ns" { rst rst~out cs2~reg0 } { 0.000ns 0.000ns 0.100ns } { 0.000ns 2.000ns 1.000ns } } }  } 0}  } { { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "5.500 ns" { clk en~reg0 cs2~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.500 ns" { clk clk~out en~reg0 cs2~reg0 } { 0.000ns 0.000ns 0.400ns 2.600ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" "" { Report "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd_cmp.qrpt" Compiler "lcd" "UNKNOWN" "V1" "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/db/lcd.quartus_db" { Floorplan "J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/" "" "3.100 ns" { rst cs2~reg0 } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "3.100 ns" { rst rst~out cs2~reg0 } { 0.000ns 0.000ns 0.100ns } { 0.000ns 2.000ns 1.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 09:40:05 2006 " "Info: Processing ended: Sat Jul 15 09:40:05 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}