}

//*****************************************************************************
//
//! Clears the status bits in this endpoint in device mode.
//!
//! \param ulBase specifies the USB module base address.
//! \param ulEndpoint is the endpoint to access.
//! \param ulFlags are the status bits that will be cleared.
//!
//! This function will clear the status of any bits that are passed in the
//! \e ulFlags parameter.  The \e ulFlags parameter can take the value returned
//! from the USBEndpointStatus() call.
//!
//! \note This function should only be called in device mode.
//!
//! \return None.
//
//*****************************************************************************
void
USBDevEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint,
                          unsigned long ulFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == USB0_BASE);
    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));

    //
    // If this is endpoint 0 then the bits have different meaning and map into
    // the TX memory location.
    //
    if(ulEndpoint == USB_EP_0)
    {
        //
        // Set the Serviced RxPktRdy bit to clear the RxPktRdy.
        //
        if(ulFlags & USB_DEV_EP0_OUT_PKTRDY)
        {
            HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_RXRDYC;
        }

        //
        // Set the serviced Setup End bit to clear the SetupEnd status.
        //
        if(ulFlags & USB_DEV_EP0_SETUP_END)
        {
            HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_SETENDC;
        }

        //
        // Clear the Sent Stall status flag.
        //
        if(ulFlags & USB_DEV_EP0_SENT_STALL)
        {
            HWREGB(ulBase + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL);
        }
    }
    else
    {
        //
        // Clear out any TX flags that were passed in.  Only
        // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN should be cleared.
        //
        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &=
            ~(ulFlags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN));

        //
        // Clear out valid RX flags that were passed in.  Only
        // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN
        // should be cleared.
        //
        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
            ~((ulFlags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR |
                          USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT);
    }
}

//*****************************************************************************
//
//! Sets the value data toggle on an endpoint in host mode.
//!
//! \param ulBase specifies the USB module base address.
//! \param ulEndpoint specifies the endpoint to reset the data toggle.
//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1.
//! \param ulFlags specifies whether to set the IN or OUT endpoint.
//!
//! This function is used to force the state of the data toggle in host mode.
//! If the value passed in the \e bDataToggle parameter is \b false, then the
//! data toggle will be set to the DATA0 state, and if it is \b true it will be
//! set to the DATA1 state.  The \e ulFlags parameter can be \b USB_EP_HOST_IN
//! or \b USB_EP_HOST_OUT to access the desired portion of this endpoint.  The
//! \e ulFlags parameter is ignored for endpoint zero.
//!
//! \note This function should only be called in host mode.
//!
//! \return None.
//
//*****************************************************************************
void
USBHostEndpointDataToggle(unsigned long ulBase, unsigned long ulEndpoint,
                          tBoolean bDataToggle, unsigned long ulFlags)
{
    unsigned long ulDataToggle;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == USB0_BASE);
    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));

    //
    // The data toggle defaults to DATA0.
    //
    ulDataToggle = 0;

    //
    // See if the data toggle should be set to DATA1.
    //
    if(bDataToggle)
    {
        //
        // Select the data toggle bit based on the endpoint.
        //
        if(ulEndpoint == USB_EP_0)
        {
            ulDataToggle = USB_CSRH0_DT;
        }
        else if(ulFlags == USB_EP_HOST_IN)
        {
            ulDataToggle = USB_RXCSRH1_DT;
        }
        else
        {
            ulDataToggle = USB_TXCSRH1_DT;
        }
    }

    //
    // Set the data toggle based on the endpoint.
    //
    if(ulEndpoint == USB_EP_0)
    {
        //
        // Set the write enable and the bit value for endpoint zero.
        //
        HWREGB(ulBase + USB_O_CSRH0) =
            ((HWREGB(ulBase + USB_O_CSRH0) &
              ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) |
             (ulDataToggle | USB_CSRH0_DTWE));
    }
    else if(ulFlags == USB_EP_HOST_IN)
    {
        //
        // Set the Write enable and the bit value for an IN endpoint.
        //
        HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) =
            ((HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) &
              ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) |
             (ulDataToggle | USB_RXCSRH1_DTWE));
    }
    else
    {
        //
        // Set the Write enable and the bit value for an OUT endpoint.
        //
        HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) =
            ((HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) &
              ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) |
             (ulDataToggle | USB_TXCSRH1_DTWE));
    }
}

//*****************************************************************************
//
//! Sets the Data toggle on an endpoint to zero.
//!
//! \param ulBase specifies the USB module base address.
//! \param ulEndpoint specifies the endpoint to reset the data toggle.
//! \param ulFlags specifies whether to access the IN or OUT endpoint.
//!
//! This function will cause the controller to clear the data toggle for an
//! endpoint.  This call is not valid for endpoint zero and can be made with
//! host or device controllers.
//!
//! The \e ulFlags parameter should be one of \b USB_EP_HOST_OUT,
//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
//!
//! \return None.
//
//*****************************************************************************
void
USBEndpointDataToggleClear(unsigned long ulBase, unsigned long ulEndpoint,
                           unsigned long ulFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == USB0_BASE);
    ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
           (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
           (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
           (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
           (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
           (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
           (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
           (ulEndpoint == USB_EP_15));

    //
    // See if the transmit or receive data toggle should be cleared.
    //
    if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
    {
        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
            USB_TXCSRL1_CLRDT;
    }
    else
    {
        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
            USB_RXCSRL1_CLRDT;
    }
}

//*****************************************************************************
//
//! Stalls the specified endpoint in device mode.
//!
//! \param ulBase specifies the USB module base address.
//! \param ulEndpoint specifies the endpoint to stall.
//! \param ulFlags specifies whether to stall the IN or OUT endpoint.
//!
//! This function will cause to endpoint number passed in to go into a stall
//! condition.  If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall
//! will be issued on the IN portion of this endpoint.  If the \e ulFlags
//! parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT
//! portion of this endpoint.
//!
//! \note This function should only be called in device mode.
//!
//! \return None.
//
//*****************************************************************************
void
USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint,
                    unsigned long ulFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == USB0_BASE);
    ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0)
    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));

    //
    // Determine how to stall this endpoint.
    //
    if(ulEndpoint == USB_EP_0)
    {
        //
        // Perform a stall on endpoint zero.
        //
        HWREGB(ulBase + USB_O_CSRL0) |=
            (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
    }
    else if(ulFlags == USB_EP_DEV_IN)
    {
        //
        // Perform a stall on an IN endpoint.
        //
        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
            USB_TXCSRL1_STALL;
    }
    else
    {
        //
        // Perform a stall on an OUT endpoint.
        //
        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
            USB_RXCSRL1_STALL;
    }
}

//*****************************************************************************
//
//! Clears the stall condition on the specified endpoint in device mode.
//!
//! \param ulBase specifies the USB module base address.
//! \param ulEndpoint specifies which endpoint to remove the stall condition.
//! \param ulFlags specifies whether to remove the stall condition from the IN
//! or the OUT portion of this endpoint.
//!
//! This function will cause the endpoint number passed in to exit the stall
//! condition.  If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall
//! will be cleared on the IN portion of this endpoint.  If the \e ulFlags
//! parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT
//! portion of this endpoint.
//!
//! \note This function should only be called in device mode.
//!
//! \return None.
//
//*****************************************************************************
void
USBDevEndpointStallClear(unsigned long ulBase, unsigned long ulEndpoint,
                         unsigned long ulFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == USB0_BASE);
    ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
           (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
           (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
           (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
           (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
           (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
           (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
           (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
    ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0)

    //
    // Determine how to clear the stall on this endpoint.
    //
    if(ulEndpoint == USB_EP_0)
    {
        //
        // Clear the stall on endpoint zero.
        //
        HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_STALLED;
    }
    else if(ulFlags == USB_EP_DEV_IN)
    {
        //
        // Clear the stall on an IN endpoint.
        //
        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &=
            ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);

        //
        // Reset the data toggle.
        //
        HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
            USB_TXCSRL1_CLRDT;
    }
    else
    {
        //
        // Clear the stall on an OUT endpoint.
        //
        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
            ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);

        //
        // Reset the data toggle.
        //
        HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
            USB_TXCSRL1_CLRDT;
    }
}

//*****************************************************************************
//
//! Connects the USB controller to the bus in device mode.
//!
//! \param ulBase specifies the USB module base address.
//!