else		if(this_ptr_set)	pointer_r <= #1 de_csr[31:4];	   end	else				pointer_r <= #1 1'b0;always @(posedge clk)	if(CH_EN & HAVE_ED)	   begin		if(this_ptr_set)	pointer_sr <= #1 pointer_r;	   end	else				pointer_sr <= #1 1'b0;// ---------------------------------------------------// CSRalways @(posedge clk or negedge rst)	if(!rst)			ch_csr_r <= #1 1'b0;	else	if(CH_EN)	   begin		if(ch_csr_we)		ch_csr_r <= #1 wb_rf_din[8:0];		else		   begin			if(ch_done_we)	ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;			if(ch_csr_dewe)	ch_csr_r[4:1] <= #1 de_csr[19:16];		   end	   end// done bitalways @(posedge clk or negedge rst)	if(!rst)		ch_done <= #1 1'b0;	else	if(CH_EN)	   begin		if(ch_csr_we)		ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];		else		if(ch_done_we)		ch_done <= #1 1'b1;	   end// busy bitalways @(posedge clk)	ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy;// stop bitalways @(posedge clk)	ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP];// error bitalways @(posedge clk or negedge rst)	if(!rst)			ch_err <= #1 1'b0;	else	if(CH_EN)	   begin		if(ch_err_we)		ch_err <= #1 1'b1;		else		if(ch_csr_re)		ch_err <= #1 1'b0;	   end// Priority Bitsalways @(posedge clk or negedge rst)	if(!rst)			ch_csr_r2 <= #1 3'h0;	else	if(CH_EN & ch_csr_we)		ch_csr_r2 <= #1 wb_rf_din[15:13];// Restart Enable Bit (REST)always @(posedge clk or negedge rst)	if(!rst)			rest_en <= #1 1'b0;	else	if(CH_EN & ch_csr_we)		rest_en <= #1 wb_rf_din[16];// INT Maskalways @(posedge clk or negedge rst)	if(!rst)			ch_csr_r3 <= #1 3'h0;	else	if(CH_EN & ch_csr_we)		ch_csr_r3 <= #1 wb_rf_din[19:17];// INT Sourcealways @(posedge clk or negedge rst)	if(!rst)			int_src_r[2] <= #1 1'b0;	else	if(CH_EN)	   begin		if(chunk_done_we)	int_src_r[2] <= #1 1'b1;		else		if(ch_csr_re)		int_src_r[2] <= #1 1'b0;	   endalways @(posedge clk or negedge rst)	if(!rst)			int_src_r[1] <= #1 1'b0;	else	if(CH_EN)	   begin		if(ch_done_we)		int_src_r[1] <= #1 1'b1;		else		if(ch_csr_re)		int_src_r[1] <= #1 1'b0;	   endalways @(posedge clk or negedge rst)	if(!rst)			int_src_r[0] <= #1 1'b0;	else	if(CH_EN)	   begin		if(ch_err_we)		int_src_r[0] <= #1 1'b1;		else		if(ch_csr_re)		int_src_r[0] <= #1 1'b0;	   end// Interrupt Outputassign int = |(int_src_r & ch_csr_r3) & CH_EN;// ---------------------------------------------------// TXZSalways @(posedge clk)	if(CH_EN)	   begin		if(ch_txsz_we)					{ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};		else		if(ch_txsz_dewe)			ch_tot_sz_r <= #1 de_txsz;		else		if(ch_rl)			{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;	   end// txsz shadow registeralways @(posedge clk)	if(CH_EN & HAVE_ARS)	   begin		if(ch_txsz_we)	ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};		else		if(rest_en & ch_txsz_dewe & de_fetch_descr)				ch_txsz_s[11:0] <= #1 de_txsz[11:0];	   end// Infinite Size indicatoralways @(posedge clk)	if(CH_EN)	   begin		if(ch_txsz_we)		ch_sz_inf <= #1 wb_rf_din[15];	   end	// ---------------------------------------------------// ADR0always @(posedge clk)	if(CH_EN)	   begin		if(ch_adr0_we)		ch_adr0_r <= #1 wb_rf_din[31:2];		else		if(ch_adr0_dewe)	ch_adr0_r <= #1 de_adr0[31:2];		else		if(ch_rl)		ch_adr0_r <= #1 ch_adr0_s;	   end// Adr0 shadow registeralways @(posedge clk)	if(CH_EN & HAVE_ARS)	   begin		if(ch_adr0_we)	ch_adr0_s <= #1 wb_rf_din[31:2];		else		if(rest_en & ch_adr0_dewe & de_fetch_descr)				ch_adr0_s <= #1 de_adr0[31:2];	   end// ---------------------------------------------------// AM0always @(posedge clk or negedge rst)	if(!rst)		ch_am0_r <= #1 28'hfffffff;	else	if(ch_am0_we)		ch_am0_r <= #1 wb_rf_din[31:4];// ---------------------------------------------------// ADR1always @(posedge clk)	if(CH_EN)	   begin		if(ch_adr1_we)		ch_adr1_r <= #1 wb_rf_din[31:2];		else		if(ch_adr1_dewe)	ch_adr1_r <= #1 de_adr1[31:2];		else		if(ch_rl)		ch_adr1_r <= #1 ch_adr1_s;	   end// Adr1 shadow registeralways @(posedge clk)	if(CH_EN & HAVE_ARS)	   begin		if(ch_adr1_we)	ch_adr1_s <= #1 wb_rf_din[31:2];		else		if(rest_en & ch_adr1_dewe & de_fetch_descr)				ch_adr1_s <= #1 de_adr1[31:2];	   end// ---------------------------------------------------// AM1always @(posedge clk or negedge rst)	if(!rst)				ch_am1_r <= #1 28'hfffffff;	else	if(ch_am1_we & CH_EN & HAVE_CBUF)	ch_am1_r <= #1 wb_rf_din[31:4];// ---------------------------------------------------// Software Pointeralways @(posedge clk or negedge rst)	if(!rst)				sw_pointer_r <= #1 28'h0;	else	if(sw_pointer_we & CH_EN & HAVE_CBUF)	sw_pointer_r <= #1 wb_rf_din[31:4];// ---------------------------------------------------// Software Pointer Match logicassign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];always @(posedge clk)	ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31];endmodulemodule wb_dma_ch_rf_dummy(clk, rst,			pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,			ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,			wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,			// DMA Registers Write Back Channel Select			ch_sel, ndnr,			// DMA Engine Status			dma_busy, dma_err, dma_done, dma_done_all,			// DMA Engine Reg File Update ctrl signals			de_csr, de_txsz, de_adr0, de_adr1,			de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,			de_fetch_descr, dma_rest,			ptr_set		);parameter	CH_NO = 0;parameter	HAVE_ARS = 1;parameter	HAVE_ED  = 1;parameter	HAVE_CBUF= 1;input		clk, rst;output	[31:0]	pointer;output	[31:0]	pointer_s;output	[31:0]	ch_csr;output	[31:0]	ch_txsz;output	[31:0]	ch_adr0;output	[31:0]	ch_adr1;output	[31:0]	ch_am0;output	[31:0]	ch_am1;output	[31:0]	sw_pointer;output		ch_stop;output		ch_dis;output		int;input	[31:0]	wb_rf_din;input	[7:0]	wb_rf_adr;input		wb_rf_we;input		wb_rf_re;input	[4:0]	ch_sel;input		ndnr;// DMA Engine Statusinput		dma_busy, dma_err, dma_done, dma_done_all;// DMA Engine Reg File Update ctrl signalsinput	[31:0]	de_csr;input	[11:0]	de_txsz;input	[31:0]	de_adr0;input	[31:0]	de_adr1;input		de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;input		de_fetch_descr;input		dma_rest;assign		pointer = 32'h0;assign		pointer_s = 32'h0;assign		ch_csr = 32'h0;assign		ch_txsz = 32'h0;assign		ch_adr0 = 32'h0;assign		ch_adr1 = 32'h0;assign		ch_am0 = 32'h0;assign		ch_am1 = 32'h0;assign		sw_pointer = 32'h0;assign		ch_stop = 1'b0;assign		ch_dis = 1'b0;assign		int = 1'b0;endmodule