;**************************************************************************************************
;*                                                                          
;* Copyright (c) 2001 - 2003 Winbond Electronics Corp. All rights reserved.      
;*                                                                         
;* FILENAME
;*     meminit.s
;*
;* VERSION
;*     1.0
;*
;* DESCRIPTION
;*     This program demonstrates how to initial W90N740 Memory controller. It will to loaded to 
;*     the on-chip RAM (0xFFE00000) for executing.
;*
;* DATA STRUCTURES
;*     None
;*
;* FUNCTIONS
;*     None
;*
;* HISTORY
;*     04/10/2003		 Created by PC30 WSChang
;*
;*     04/21/2003        V1.0 Modified by PC30 MNCheng
;*
;* REMARK
;*     None
;*     
; *************************************************************************************************

regPDID		EQU		0xFFF00000	;Product Identifier Register

;*********************************************************************************************
;*
;* EBI Control Registers
;*
;*********************************************************************************************
regEBICON	EQU		0xFFF01000	;EBI control register 
regROMCON	EQU		0xFFF01004	;ROM/FLASH control register 
regSDCONF0	EQU		0xFFF01008	;SDRAM bank 0 configuration register 
regSDCONF1	EQU		0xFFF0100C	;SDRAM bank 1 configuration register 
regSDTIME0	EQU		0xFFF01010	;SDRAM bank 0 timing control register  
regSDTIME1	EQU		0xFFF01014	;SDRAM bank 1 timing control register  
regEXT0CON	EQU		0xFFF01018	;External I/O 0 control register 
regEXT1CON	EQU		0xFFF0101C	;External I/O 1 control register 
regEXT2CON	EQU		0xFFF01020	;External I/O 2 control register  
regEXT3CON	EQU		0xFFF01024	;External I/O 3 control register 
regCKSKEW	EQU		0xFFF01F00	;Clock skew control register 

    
	AREA MEM_INIT, CODE, READONLY
	ENTRY
	
; Set up the bootROM & DRAM Bank0 & DRAM Bank1
 	LDR	r0, =MEM_CONFG   ; point the parameters address
	LDR	r1, =regEBICON   ; point to the registers address
	LDMFD	r0,{r2-r7}   ; load the parameters
	STMIA	r1,{r2-r7}   ; write to the registers

; Set up External Bank 0
	LDR	r0,=0x08003FFE   ; base=0x4000000, size=256KB, 16-bit
	LDR	r1,=regEXT0CON
	STR	r0,[r1]
	
; Set up other External Banks if necessary
	;;;

; Adjust clock skew

    ; Check version number of W90N740 to set the clock skew
    LDR		r0, =regPDID     ; Product Identifier Register
    LDR		r0, [r0]    
    LDR		r1, =0x3F000000  ; bit 29 ~ 24
    ANDS	r0,r0,r1
    BEQ		version0
    LDR		r1, =0x01000000
    CMP		r0, r1
    BEQ		version1
    B		unknow_version
version0
	LDR		r0, =0x0FF007A
    B		update_clkskew
version1    
	LDR		r0, =0x0FF0039
    B		update_clkskew
update_clkskew
	LDR		r1, =regCKSKEW
	STR		r0,[r1]		
unknow_version
	
	
	MOV		r0,#0x18
	SWI		0x123456  ; exit
	
0	B	%0

MEM_CONFG
	DCD	0x000509c0    ; EBICON : auto-refresh, clock enable
	DCD	0xfe020FF0    ; ROMCON : base=0x7F000000, size=1MB, 
	DCD	0x000090e3    ; SDCONF0: base=0, size=8MB, 32-bit, col=10
	DCD	0x00000000    ; SDCONF1: disabled.
	DCD	0x00000292    ; SDTIME0: tRCD=3, tRDL=3, tRP=3, tRAS=3 MCLKs
	DCD	0x00000000    ; SDTIME1: N/A

	END