?? 740defs.h
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/**************************************************************************************************
*
* Copyright (c) 2001 - 2003 Winbond Electronics Corp. All rights reserved.
*
* FILENAME
* w90n740.h
*
* VERSION
* 1.0
*
* DESCRIPTION
* This file contains the register map of W90N740 processor.
*
* DATA STRUCTURES
* None
*
* FUNCTIONS
* None
*
* HISTORY
* 04/10/2003 Ver 1.0 Created by PC30 MNCheng
*
* REMARK
* None
*
*************************************************************************************************/
#ifndef _W90N740_H
#define _W90N740_H
typedef char int8;
typedef unsigned char uint8;
typedef short int16;
typedef unsigned short uint16;
typedef int int32;
typedef unsigned int uint32;
typedef unsigned int UINT;
#define S8 signed char
#define S16 signed short
#define S32 signed int
#define U8 unsigned char
#define U16 unsigned short
#define U32 unsigned int
#define REG8 volatile unsigned char
#define REG16 volatile unsigned short
#define REG32 volatile unsigned int
#define BYTE U8
#define VPint *(volatile unsigned int *)
#define VPshort *(volatile unsigned short *)
#define VPchar *(volatile unsigned char *)
#define outpw(port,value) port=value
#define inpw(port) port
/* system base address */
#define AHB_IO_BASE 0xFFF00000
#define APB_IO_BASE 0xFFF80000
/* OSC freq. */
#define EXT_CLOCK_RATE 15000000L
/****************************************************************************************************
*
* System Manager Control Registers
*
****************************************************************************************************/
#define PDID (VPint(AHB_IO_BASE+0x0000)) /* Product Identifier Register */
#define ARBCON (VPint(AHB_IO_BASE+0x0004)) /* Arbitration Control Register */
#define PLLCON (VPint(AHB_IO_BASE+0x0008)) /* PLL Control Register */
#define CLKSEL (VPint(AHB_IO_BASE+0x000C)) /* Clock Select Register */
/****************************************************************************************************
*
* EBI Control Registers
*
****************************************************************************************************/
#define EBICON (VPint(AHB_IO_BASE+0x1000)) /* EBI control register */
#define ROMCON (VPint(AHB_IO_BASE+0x1004)) /* ROM/FLASH control register */
#define SDCONF0 (VPint(AHB_IO_BASE+0x1008)) /* SDRAM bank 0 configuration register */
#define SDCONF1 (VPint(AHB_IO_BASE+0x100C)) /* SDRAM bank 1 configuration register */
#define SDTIME0 (VPint(AHB_IO_BASE+0x1010)) /* SDRAM bank 0 timing control register */
#define SDTIME1 (VPint(AHB_IO_BASE+0x1014)) /* SDRAM bank 1 timing control register */
#define EXT0CON (VPint(AHB_IO_BASE+0x1018)) /* External I/O 0 control register */
#define EXT1CON (VPint(AHB_IO_BASE+0x101C)) /* External I/O 1 control register */
#define EXT2CON (VPint(AHB_IO_BASE+0x1020)) /* External I/O 2 control register */
#define EXT3CON (VPint(AHB_IO_BASE+0x1024)) /* External I/O 3 control register */
#define CKSKEW (VPint(AHB_IO_BASE+0x1F00)) /* Clock skew control register */
/****************************************************************************************************
*
* Cache Controller Registers
*
****************************************************************************************************/
#define CAHCNF (VPint(AHB_IO_BASE+0x2000)) /* cache configuration register */
#define CAHCON (VPint(AHB_IO_BASE+0x2004)) /* cache control register */
/* Routines to control I/D-Cache */
#define Flush_Cache() CAHCON = 0x87; while (CAHCON & 0x87) ;
#define TurnOn_Cache() CAHCNF = 0x07; /* 2:write buffer, 1:D-cache, 0:I-cache */
#define TurnOff_Cache() CAHCNF = 0;
/****************************************************************************************************
*
* MAC Registers
*
****************************************************************************************************/
/* MAC 0 */
#define CAMCMR_0 (VPint(AHB_IO_BASE+0x3000)) /* CAM Registers */
#define CAMEN_0 (VPint(AHB_IO_BASE+0x3004))
#define CAM0M_Base_0 AHB_IO_BASE+0x3008
#define CAM0L_Base_0 AHB_IO_BASE+0x300c
#define CAMxM_Reg_0(x) (VPint(CAM0M_Base_0+x*0x8))
#define CAMxL_Reg_0(x) (VPint(CAM0L_Base_0+x*0x8))
#define MIEN_0 (VPint(AHB_IO_BASE+0x3088)) /* MAC Registers */
#define MCMDR_0 (VPint(AHB_IO_BASE+0x308c))
#define MIID_0 (VPint(AHB_IO_BASE+0x3090))
#define MIIDA_0 (VPint(AHB_IO_BASE+0x3094))
#define MPCNT_0 (VPint(AHB_IO_BASE+0x3098))
#define TXDLSA_0 (VPint(AHB_IO_BASE+0x309c)) /* DMA Registers */
#define RXDLSA_0 (VPint(AHB_IO_BASE+0x30a0))
#define DMARFC_0 (VPint(AHB_IO_BASE+0x30a4))
#define TSDR_0 (VPint(AHB_IO_BASE+0x30a8))
#define RSDR_0 (VPint(AHB_IO_BASE+0x30ac))
#define FIFOTHD_0 (VPint(AHB_IO_BASE+0x30b0)) /* Test Registers */
/* Status Registers */
#define MISTA_0 (VPint(AHB_IO_BASE+0x30b4)) /* MAC Registers */
#define MGSTA_0 (VPint(AHB_IO_BASE+0x30b8))
#define MRPC_0 (VPint(AHB_IO_BASE+0x30bc))
#define MRPCC_0 (VPint(AHB_IO_BASE+0x30c0))
#define MREPC_0 (VPint(AHB_IO_BASE+0x30c4))
#define DMARFS_0 (VPint(AHB_IO_BASE+0x30c8)) /* DMA Registers */
#define CTXDSA_0 (VPint(AHB_IO_BASE+0x30cc))
#define CTXBSA_0 (VPint(AHB_IO_BASE+0x30d0))
#define CRXDSA_0 (VPint(AHB_IO_BASE+0x30d4))
#define CRXBSA_0 (VPint(AHB_IO_BASE+0x30d8))
/* Diagnostic Registers */
#define TICS_0 (VPint(AHB_IO_BASE+0x3100)) /* Test Registers */
#define RXFSM_0 (VPint(AHB_IO_BASE+0x3200)) /* Debug Registers */
#define TXFSM_0 (VPint(AHB_IO_BASE+0x3204))
#define FSM0_0 (VPint(AHB_IO_BASE+0x3208))
#define FSM1_0 (VPint(AHB_IO_BASE+0x320c))
#define DCR_0 (VPint(AHB_IO_BASE+0x3210))
#define BISTR_0 (VPint(AHB_IO_BASE+0x3300)) /* BIST Registers */
/* MAC 1 */
#define CAMCMR_1 (VPint(AHB_IO_BASE+0x3800)) /* CAM Registers */
#define CAMEN_1 (VPint(AHB_IO_BASE+0x3804))
#define CAM0M_Base_1 AHB_IO_BASE+0x3808
#define CAM0L_Base_1 AHB_IO_BASE+0x380c
#define CAMxM_Reg_1(x) (VPint(CAM0M_Base_1+x*0x8))
#define CAMxL_Reg_1(x) (VPint(CAM0L_Base_1+x*0x8))
#define MIEN_1 (VPint(AHB_IO_BASE+0x3888)) /* MAC Registers */
#define MCMDR_1 (VPint(AHB_IO_BASE+0x388c))
#define MIID_1 (VPint(AHB_IO_BASE+0x3890))
#define MIIDA_1 (VPint(AHB_IO_BASE+0x3894))
#define MPCNT_1 (VPint(AHB_IO_BASE+0x3898))
#define TXDLSA_1 (VPint(AHB_IO_BASE+0x389c)) /* DMA Registers */
#define RXDLSA_1 (VPint(AHB_IO_BASE+0x38a0))
#define DMARFC_1 (VPint(AHB_IO_BASE+0x38a4))
#define TSDR_1 (VPint(AHB_IO_BASE+0x38a8))
#define RSDR_1 (VPint(AHB_IO_BASE+0x38ac))
#define FIFOTHD_1 (VPint(AHB_IO_BASE+0x38b0)) /* Test Registers */
/* Status Registers */
#define MISTA_1 (VPint(AHB_IO_BASE+0x38b4)) /* MAC Registers */
#define MGSTA_1 (VPint(AHB_IO_BASE+0x38b8))
#define MRPC_1 (VPint(AHB_IO_BASE+0x38bc))
#define MRPCC_1 (VPint(AHB_IO_BASE+0x38c0))
#define MREPC_1 (VPint(AHB_IO_BASE+0x38c4))
#define DMARFS_1 (VPint(AHB_IO_BASE+0x38c8)) /* DMA Registers */
#define CTXDSA_1 (VPint(AHB_IO_BASE+0x38cc))
#define CTXBSA_1 (VPint(AHB_IO_BASE+0x38d0))
#define CRXDSA_1 (VPint(AHB_IO_BASE+0x38d4))
#define CRXBSA_1 (VPint(AHB_IO_BASE+0x38d8))
/* Diagnostic Registers */
#define TICS_1 (VPint(AHB_IO_BASE+0x3900)) /* Test Registers */
#define RXFSM_1 (VPint(AHB_IO_BASE+0x3a00)) /* Debug Registers */
#define TXFSM_1 (VPint(AHB_IO_BASE+0x3a04))
#define FSM0_1 (VPint(AHB_IO_BASE+0x3a08))
#define FSM1_1 (VPint(AHB_IO_BASE+0x3a0c))
#define DCR_1 (VPint(AHB_IO_BASE+0x3a10))
#define BISTR_1 (VPint(AHB_IO_BASE+0x3b00)) /* BIST Registers */
/****************************************************************************************************
*
* GDMA Registers
*
****************************************************************************************************/
#define GDMA_CTL0 (VPint(AHB_IO_BASE+0x4000)) /* Channel 0 Control Register */
#define GDMA_SRCB0 (VPint(AHB_IO_BASE+0x4004)) /* Channel 0 Source Base Address Register */
#define GDMA_DSTB0 (VPint(AHB_IO_BASE+0x4008)) /* Channel 0 Destination Base Address Register */
#define GDMA_TCNT0 (VPint(AHB_IO_BASE+0x400C)) /* Channel 0 Transfer Count Register */
#define GDMA_CSRC0 (VPint(AHB_IO_BASE+0x4010)) /* Channel 0 Current Source Address Register */
#define GDMA_CDST0 (VPint(AHB_IO_BASE+0x4014)) /* Channel 0 Current Destination Address Register */
#define GDMA_CTCNT0 (VPint(AHB_IO_BASE+0x4018)) /* Channel 0 Current Transfer Count Register */
#define GDMA_CTL1 (VPint(AHB_IO_BASE+0x4020)) /* Channel 1 Control Register */
#define GDMA_SRCB1 (VPint(AHB_IO_BASE+0x4024)) /* Channel 1 Source Base Address Register */
#define GDMA_DSTB1 (VPint(AHB_IO_BASE+0x4028)) /* Channel 1 Destination Base Address Register */
#define GDMA_TCNT1 (VPint(AHB_IO_BASE+0x402C)) /* Channel 1 Transfer Count Register */
#define GDMA_CSRC1 (VPint(AHB_IO_BASE+0x4030)) /* Channel 1 Current Source Address Register */
#define GDMA_CDST1 (VPint(AHB_IO_BASE+0x4034)) /* Channel 1 Current Destination Address Register */
#define GDMA_CTCNT1 (VPint(AHB_IO_BASE+0x4038)) /* Channel 1 Current Transfer Count Register */
/****************************************************************************************************
*
* UART Control Registers
*
****************************************************************************************************/
#define UART_TX (VPint(APB_IO_BASE+0x0000)) /* (W) TX buffer */
#define UART_RX (VPint(APB_IO_BASE+0x0000)) /* (R) RX buffer */
#define UART_LSB (VPint(APB_IO_BASE+0x0000)) /* Divisor latch LSB */
#define UART_MSB (VPint(APB_IO_BASE+0x0004)) /* Divisor latch MSB */
#define UART_IER (VPint(APB_IO_BASE+0x0004)) /* Interrupt enable register */
#define UART_IIR (VPint(APB_IO_BASE+0x0008)) /* (R) Interrupt ident. register */
#define UART_FCR (VPint(APB_IO_BASE+0x0008)) /* (W) FIFO control register */
#define UART_LCR (VPint(APB_IO_BASE+0x000C)) /* Line control register */
#define UART_MCR (VPint(APB_IO_BASE+0x0010)) /* Modem control register */
#define UART_LSR (VPint(APB_IO_BASE+0x0014)) /* (R) Line status register */
#define UART_MSR (VPint(APB_IO_BASE+0x0018)) /* (R) Modem status register */
#define UART_TOR (VPint(APB_IO_BASE+0x001C)) /* (R) Time out register */
/****************************************************************************************************
*
* Timer Control Registers
*
****************************************************************************************************/
#define TCR0 (VPint(APB_IO_BASE+0x1000)) /* Timer Control Register 0 */
#define TCR1 (VPint(APB_IO_BASE+0x1004)) /* Timer Control Register 1 */
#define TICR0 (VPint(APB_IO_BASE+0x1008)) /* Timer Initial Control Register 0 */
#define TICR1 (VPint(APB_IO_BASE+0x100C)) /* Timer Initial Control Register 1 */
#define TDR0 (VPint(APB_IO_BASE+0x1010)) /* Timer Data Register 0 */
#define TDR1 (VPint(APB_IO_BASE+0x1014)) /* Timer Data Register 1 */
#define TISR (VPint(APB_IO_BASE+0x1018)) /* Timer Interrupt Status Register */
#define WTCR (VPint(APB_IO_BASE+0x101C)) /* Watchdog Timer Control Register */
#define TICKS_PER_SEC 100
/****************************************************************************************************
*
* Advanced Interrupt Controller Registers
*
****************************************************************************************************/
#define AIC_SCR_TIMER0 (VPint(APB_IO_BASE+0x201C)) /* Source Control Register 7 */
#define AIC_SCR_TIMER1 (VPint(APB_IO_BASE+0x2020)) /* Source Control Register 8 */
#define AIC_IRSR (VPint(APB_IO_BASE+0x2100)) /* Interrupt Raw Status Register */
#define AIC_IASR (VPint(APB_IO_BASE+0x2104)) /* Interrupt Active Status Register */
#define AIC_ISR (VPint(APB_IO_BASE+0x2108)) /* Interrupt Status Register */
#define AIC_IPER (VPint(APB_IO_BASE+0x210c)) /* Interrupt Priority Encoding Register */
#define AIC_ISNR (VPint(APB_IO_BASE+0x2110)) /* Interrupt Source Number Register */
#define AIC_IMR (VPint(APB_IO_BASE+0x2114)) /* Interrupt Mask Register */
#define AIC_OISR (VPint(APB_IO_BASE+0x2118)) /* Output Interrupt Status Register */
#define AIC_MECR (VPint(APB_IO_BASE+0x2120)) /* Mask Enable Command Register */
#define AIC_MDCR (VPint(APB_IO_BASE+0x2124)) /* Mask Disable Command Register */
#define AIC_SSCR (VPint(APB_IO_BASE+0x2128)) /* Source Set Command Register */
#define AIC_SCCR (VPint(APB_IO_BASE+0x212c)) /* Source Clear Command Register */
#define AIC_EOSCR (VPint(APB_IO_BASE+0x2130)) /* End of Service Command Register */
/* Internal interrupt Source */
#define TIMERINT0 7 /* Timer interrupt 0 */
#define TIMERINT1 8 /* Timer interrupt 1 */
#define EMCTXINT0 13 /* EMC TX interrupt 0 */
#define EMCTXINT1 14 /* EMC TX interrupt 1 */
#define EMCRXINT0 15 /* EMC RX interrupt 0 */
#define EMCRXINT1 16 /* EMC RX interrupt 1 */
#define GDMAINT0 17 /* GDMA Channel Interrupt 0 */
#define GDMAINT1 18 /* GDMA Channel Interrupt 1 */
/* Routines to Enable/Disable Interrupts */
#define Enable_Int(n) AIC_MECR = (1<<(n))
#define Disable_Int(n) AIC_MDCR = (1<<(n))
#define Enable_Int_All() AIC_MECR = 0xFFFF
#define Disable_Int_All() AIC_MDCR = 0xFFFF
/* */
extern void SetIntISR(int, void (*)());
extern __irq void IRQ_IntHandler();
extern int UART_Initialize();
extern volatile uint32 cur_ticks;
#endif /* _W90N740_H */?? 快捷鍵說明
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