?? design rule check - lesson10.drc
字號:
Protel Design System Design Rule Check
PCB File : C:\Documents and Settings\gggg\我的文檔\lesson10\lesson10.PcbDoc
Date : 2007-2-1
Time : 11:56:20
Processing Rule : Width Constraint (Min=20mil) (Max=20mil) (Preferred=20mil) (InNet('GND'))
Rule Violations :0
Processing Rule : Width Constraint (Min=20mil) (Max=20mil) (Preferred=20mil) (InNet('VCC'))
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Violation between Via (2355mil,3840mil) Top Layer to Bottom Layer
Violation between Via (2355mil,1735mil) Top Layer to Bottom Layer
Violation between Via (4575mil,1745mil) Top Layer to Bottom Layer
Violation between Via (4540mil,3795mil) Top Layer to Bottom Layer
Rule Violations :4
Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=12mil) (Max=12mil) (Preferred=12mil) (All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=12mil) (All),(All)
Rule Violations :0
Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Violations Detected : 4
Time Elapsed : 00:00:00?? 快捷鍵說明
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