/* ==================================================================================
File name:        regs240x.h                     
                    
Originator: Digital Control Systems Group
            Texas Instruments

Description:   F240x register definitions.
=====================================================================================
 History:
-------------------------------------------------------------------------------------
 9-15-2000  Release Rev 1.0                                                  
---------------------------------------------------------------------------------- */

#ifndef __REGS240X_H__
#define __REGS240X_H__



#define IMR                *((volatile int *)0x0004)    /*   Interrupt Mask Register             */
#define IFR                *((volatile int *)0x0006)    /*   Interrupt Flag Register             */
#define SCSR1              *((volatile int *)0x7018)    /*   System Control &  Status Reg. 1     */
#define SCSR2              *((volatile int *)0x7019)    /*   System Control &  Status Reg. 2     */
#define DINR               *((volatile int *)0x701C)    /*   Device Identification Register.     */
#define PIVR               *((volatile int *)0x701E)    /*   Peripheral Interrupt Vector Reg.    */
#define PIRQR0             *((volatile int *)0x7010)    /*   Periph Interrupt Request Reg 0.     */
#define PIRQR1             *((volatile int *)0x7011)    /*   Periph Interrupt Request Reg 1.     */
#define PIRQR2             *((volatile int *)0x7012)    /*   Periph Interrupt Request Reg 2.     */
#define PIACKR0            *((volatile int *)0x7014)    /*   Periph Interrupt Acknowledge Reg 0. */
#define PIACKR1            *((volatile int *)0x7015)    /*   Periph Interrupt Acknowledge Reg 1. */
#define PIACKR2            *((volatile int *)0x7016)    /*   Periph Interrupt Acknowledge Reg 2. */
#define XINT1CR            *((volatile int *)0x7070)    /*   Ext. interrupt 1 config reg for X241*/
#define XINT2CR            *((volatile int *)0x7071)    /*   External interrupt 2 config. X241/2/*/
#define MCRA               *((volatile int *)0x7090)    /*   Output Control Reg A                */
#define OCRA               *((volatile int *)0x7090)    /*   Output Control Reg A                */
#define MCRB               *((volatile int *)0x7092)    /*   Output Control Reg B                */
#define OCRB               *((volatile int *)0x7092)    /*   Output Control Reg B                */
#define MCRC               *((volatile int *)0x7094)    /*   Output Control Reg C                */
#define ISRA               *((volatile int *)0x7094)    /*   Input Status Reg A x240x only       */
#define ISRB               *((volatile int *)0x7096)    /*   Input Status Reg B x240x only       */
#define PADATDIR           *((volatile int *)0x7098)    /*   I/O port A Data & Direction reg.    */
#define PBDATDIR           *((volatile int *)0x709A)    /*   I/O port B Data & Direction reg.    */
#define PCDATDIR           *((volatile int *)0x709C)    /*   I/O port C Data & Direction reg.    */
#define PDDATDIR           *((volatile int *)0x709E)    /*   I/O port D Data & Direction reg.    */
#define PEDATDIR           *((volatile int *)0x7095)    /*   I/O port E Data & Direction reg.    */
#define PFDATDIR           *((volatile int *)0x7096)    /*   I/O port F Data & Direction reg.    */
#define WDCNTR             *((volatile int *)0x7023)    /*   WD Counter reg                      */
#define WDKEY              *((volatile int *)0x7025)    /*   WD Key reg                          */
#define WDCR               *((volatile int *)0x7029)    /*   WD Control reg                      */
#define ADCTRL1            *((volatile int *)0x70A0)    /*   ADC Control Reg1                    */
#define ADCTRL2            *((volatile int *)0x70A1)    /*   ADC Control Reg2                    */
#define MAXCONV            *((volatile int *)0x70A2)    /*   Maximum conversion channels register*/
#define CHSELSEQ1          *((volatile int *)0x70A3)    /*   Channel select Sequencing control re*/
#define CHSELSEQ2          *((volatile int *)0x70A4)    /*   Channel select Sequencing control re*/
#define CHSELSEQ3          *((volatile int *)0x70A5)    /*   Channel select Sequencing control re*/
#define CHSELSEQ4          *((volatile int *)0x70A6)    /*   Channel select Sequencing control re*/
#define AUTO_SEQ_SR        *((volatile int *)0x70A7)    /*   Auto-sequence status register       */
#define RESULT0            *((volatile int *)0x70A8)    /*   Conversion result buffer register 0 */
#define RESULT1            *((volatile int *)0x70A9)    /*   Conversion result buffer register 1 */
#define RESULT2            *((volatile int *)0x70AA)    /*   Conversion result buffer register 2 */
#define RESULT3            *((volatile int *)0x70AB)    /*   Conversion result buffer register 3 */
#define RESULT4            *((volatile int *)0x70AC)    /*   Conversion result buffer register 4 */
#define RESULT5            *((volatile int *)0x70AD)    /*   Conversion result buffer register 5 */
#define RESULT6            *((volatile int *)0x70AE)    /*   Conversion result buffer register 6 */
#define RESULT7            *((volatile int *)0x70AF)    /*   Conversion result buffer register 7 */
#define RESULT8            *((volatile int *)0x70B0)    /*   Conversion result buffer register 8 */
#define RESULT9            *((volatile int *)0x70B1)    /*   Conversion result buffer register 9 */
#define RESULT10           *((volatile int *)0x70B2)    /*   Conversion result buffer register 10*/
#define RESULT11           *((volatile int *)0x70B3)    /*   Conversion result buffer register 11*/
#define RESULT12           *((volatile int *)0x70B4)    /*   Conversion result buffer register 12*/
#define RESULT13           *((volatile int *)0x70B5)    /*   Conversion result buffer register 13*/
#define RESULT14           *((volatile int *)0x70B6)    /*   Conversion result buffer register 14*/
#define RESULT15           *((volatile int *)0x70B7)    /*   Conversion result buffer register 15*/
#define CALIBRATION        *((volatile int *)0x70B8)    /*   Calib result, used to correct subseq*/
#define SPICCR             *((volatile int *)0x7040)    /*   SPI Config Control Reg              */
#define SPICTL             *((volatile int *)0x7041)    /*   SPI Operation Control Reg           */
#define SPISTS             *((volatile int *)0x7042)    /*   SPI Status Reg                      */
#define SPIBRR             *((volatile int *)0x7044)    /*   SPI Baud rate control reg           */
#define SPIRXEMU           *((volatile int *)0x7046)    /*   SPI Emulation buffer reg            */
#define SPIRXBUF           *((volatile int *)0x7047)    /*   SPI Serial receive buffer reg       */
#define SPITXBUF           *((volatile int *)0x7048)    /*   SPI Serial transmit buffer reg      */
#define SPIDAT             *((volatile int *)0x7049)    /*   SPI Serial data reg                 */
#define SPIPRI             *((volatile int *)0x704F)    /*   SPI Priority control reg            */
#define SCICCR             *((volatile int *)0x7050)    /*   SCI Communication control reg       */
#define SCICTL1            *((volatile int *)0x7051)    /*   SCI Control reg1                    */
#define SCIHBAUD           *((volatile int *)0x7052)    /*   SCI Baud Rate MSbyte reg            */
#define SCILBAUD           *((volatile int *)0x7053)    /*   SCI Baud Rate LSbyte reg            */
#define SCICTL2            *((volatile int *)0x7054)    /*   SCI Control reg2                    */
#define SCIRXST            *((volatile int *)0x7055)    /*   SCI Receiver Status reg             */
#define SCIRXEMU           *((volatile int *)0x7056)    /*   SCI Emulation Data Buffer reg       */
#define SCIRXBUF           *((volatile int *)0x7057)    /*   SCI Receiver Data buffer reg        */
#define SCITXBUF           *((volatile int *)0x7059)    /*   SCI Transmit Data buffer reg        */
#define SCIPRI             *((volatile int *)0x705F)    /*   SCI Priority control reg            */
#define GPTCONA            *((volatile int *)0x7400)    /*   GP Timer control register A .       */
#define T1CNT              *((volatile int *)0x7401)    /*   GP Timer 1 counter register.        */
#define T1CMPR             *((volatile int *)0x7402)    /*   GP Timer 1 compare register.        */
#define T1PR               *((volatile int *)0x7403)    /*   GP Timer 1 period register.         */
#define T1PER              *((volatile int *)0x7403)    /*   GP Timer 1 period register.         */
#define T1CON              *((volatile int *)0x7404)    /*   GP Timer 1 control register.        */
#define T2CNT              *((volatile int *)0x7405)    /*   GP Timer 2 counter register.        */
#define T2CMPR             *((volatile int *)0x7406)    /*   GP Timer 2 compare register.        */
#define T2PR               *((volatile int *)0x7407)    /*   GP Timer 2 period register.         */
#define T2PER              *((volatile int *)0x7407)    /*   GP Timer 2 period register.         */
#define T2CON              *((volatile int *)0x7408)    /*   GP Timer 2 control register.        */
#define COMCONA            *((volatile int *)0x7411)    /*   Compare control register A.         */
#define ACTRA              *((volatile int *)0x7413)    /*   Full compare action control register*/
#define DBTCONA            *((volatile int *)0x7415)    /*   Dead-band timer control register A. */
#define CMPR1              *((volatile int *)0x7417)    /*   Full compare unit compare register1 */
#define CMPR2              *((volatile int *)0x7418)    /*   Full compare unit compare register2 */
#define CMPR3              *((volatile int *)0x7419)    /*   Full compare unit compare register3 */
#define CAPCONA            *((volatile int *)0x7420)    /*   Capture control register A.         */
#define CAPFIFOA           *((volatile int *)0x7422)    /*   Capture FIFO status register A.     */
#define CAP1FIFO           *((volatile int *)0x7423)    /*   Capture Channel 1 FIFO Top          */