?? lcdh.txt
字號:
#define ADC12CTL2_ (0x0704u) /* ADC12+ Control 2 */
DEFCW( ADC12CTL2 , ADC12CTL2_)
#define ADC12IFG_ (0x070Au) /* ADC12+ Interrupt Flag */
DEFCW( ADC12IFG , ADC12IFG_)
#define ADC12IE_ (0x070Cu) /* ADC12+ Interrupt Enable */
DEFCW( ADC12IE , ADC12IE_)
#define ADC12IV_ (0x070Eu) /* ADC12+ Interrupt Vector Word */
DEFCW( ADC12IV , ADC12IV_)
#define ADC12MEM0_ (0x0720u) /* ADC12 Conversion Memory 0 */
DEFCW( ADC12MEM0 , ADC12MEM0_)
#define ADC12MEM1_ (0x0722u) /* ADC12 Conversion Memory 1 */
DEFCW( ADC12MEM1 , ADC12MEM1_)
#define ADC12MEM2_ (0x0724u) /* ADC12 Conversion Memory 2 */
DEFCW( ADC12MEM2 , ADC12MEM2_)
#define ADC12MEM3_ (0x0726u) /* ADC12 Conversion Memory 3 */
DEFCW( ADC12MEM3 , ADC12MEM3_)
#define ADC12MEM4_ (0x0728u) /* ADC12 Conversion Memory 4 */
DEFCW( ADC12MEM4 , ADC12MEM4_)
#define ADC12MEM5_ (0x072Au) /* ADC12 Conversion Memory 5 */
DEFCW( ADC12MEM5 , ADC12MEM5_)
#define ADC12MEM6_ (0x072Cu) /* ADC12 Conversion Memory 6 */
DEFCW( ADC12MEM6 , ADC12MEM6_)
#define ADC12MEM7_ (0x072Eu) /* ADC12 Conversion Memory 7 */
DEFCW( ADC12MEM7 , ADC12MEM7_)
#define ADC12MEM8_ (0x0730u) /* ADC12 Conversion Memory 8 */
DEFCW( ADC12MEM8 , ADC12MEM8_)
#define ADC12MEM9_ (0x0732u) /* ADC12 Conversion Memory 9 */
DEFCW( ADC12MEM9 , ADC12MEM9_)
#define ADC12MEM10_ (0x0734u) /* ADC12 Conversion Memory 10 */
DEFCW( ADC12MEM10 , ADC12MEM10_)
#define ADC12MEM11_ (0x0736u) /* ADC12 Conversion Memory 11 */
DEFCW( ADC12MEM11 , ADC12MEM11_)
#define ADC12MEM12_ (0x0738u) /* ADC12 Conversion Memory 12 */
DEFCW( ADC12MEM12 , ADC12MEM12_)
#define ADC12MEM13_ (0x073Au) /* ADC12 Conversion Memory 13 */
DEFCW( ADC12MEM13 , ADC12MEM13_)
#define ADC12MEM14_ (0x073Cu) /* ADC12 Conversion Memory 14 */
DEFCW( ADC12MEM14 , ADC12MEM14_)
#define ADC12MEM15_ (0x073Eu) /* ADC12 Conversion Memory 15 */
DEFCW( ADC12MEM15 , ADC12MEM15_)
#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */
#ifndef __IAR_SYSTEMS_ICC__
#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
#else
#define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
#endif
#define ADC12MCTL0_ (0x0710u) /* ADC12 Memory Control 0 */
DEFC( ADC12MCTL0 , ADC12MCTL0_)
#define ADC12MCTL1_ (0x0711u) /* ADC12 Memory Control 1 */
DEFC( ADC12MCTL1 , ADC12MCTL1_)
#define ADC12MCTL2_ (0x0712u) /* ADC12 Memory Control 2 */
DEFC( ADC12MCTL2 , ADC12MCTL2_)
#define ADC12MCTL3_ (0x0713u) /* ADC12 Memory Control 3 */
DEFC( ADC12MCTL3 , ADC12MCTL3_)
#define ADC12MCTL4_ (0x0714u) /* ADC12 Memory Control 4 */
DEFC( ADC12MCTL4 , ADC12MCTL4_)
#define ADC12MCTL5_ (0x0715u) /* ADC12 Memory Control 5 */
DEFC( ADC12MCTL5 , ADC12MCTL5_)
#define ADC12MCTL6_ (0x0716u) /* ADC12 Memory Control 6 */
DEFC( ADC12MCTL6 , ADC12MCTL6_)
#define ADC12MCTL7_ (0x0717u) /* ADC12 Memory Control 7 */
DEFC( ADC12MCTL7 , ADC12MCTL7_)
#define ADC12MCTL8_ (0x0718u) /* ADC12 Memory Control 8 */
DEFC( ADC12MCTL8 , ADC12MCTL8_)
#define ADC12MCTL9_ (0x0719u) /* ADC12 Memory Control 9 */
DEFC( ADC12MCTL9 , ADC12MCTL9_)
#define ADC12MCTL10_ (0x071Au) /* ADC12 Memory Control 10 */
DEFC( ADC12MCTL10 , ADC12MCTL10_)
#define ADC12MCTL11_ (0x071Bu) /* ADC12 Memory Control 11 */
DEFC( ADC12MCTL11 , ADC12MCTL11_)
#define ADC12MCTL12_ (0x071Cu) /* ADC12 Memory Control 12 */
DEFC( ADC12MCTL12 , ADC12MCTL12_)
#define ADC12MCTL13_ (0x071Du) /* ADC12 Memory Control 13 */
DEFC( ADC12MCTL13 , ADC12MCTL13_)
#define ADC12MCTL14_ (0x071Eu) /* ADC12 Memory Control 14 */
DEFC( ADC12MCTL14 , ADC12MCTL14_)
#define ADC12MCTL15_ (0x071Fu) /* ADC12 Memory Control 15 */
DEFC( ADC12MCTL15 , ADC12MCTL15_)
#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */
#ifndef __IAR_SYSTEMS_ICC__
#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
#else
#define ADC12MCTL ((char*) ADC12MCTL0) /* ADC12 Memory Control (for C) */
#endif
/* ADC12CTL0 Control Bits */
#define ADC12SC (0x0001u) /* ADC12 Start Conversion */
#define ADC12ENC (0x0002u) /* ADC12 Enable Conversion */
#define ADC12TOVIE (0x0004u) /* ADC12 Timer Overflow interrupt enable */
#define ADC12OVIE (0x0008u) /* ADC12 Overflow interrupt enable */
#define ADC12ON (0x0010u) /* ADC12 On/enable */
#define ADC12REFON (0x0020u) /* ADC12 Reference on */
#define ADC12REF2_5V (0x0040u) /* ADC12 Ref 0:1.5V / 1:2.5V */
#define ADC12MSC (0x0080u) /* ADC12 Multiple SampleConversion */
#define ADC12SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
#define ADC12SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select Bit: 1 */
#define ADC12SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select Bit: 2 */
#define ADC12SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select Bit: 3 */
#define ADC12SHT10 (0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
#define ADC12SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
#define ADC12SHT12 (0x4000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
#define ADC12SHT13 (0x8000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
/* ADC12CTL0 Control Bits */
#define ADC12SC_L (0x0001u) /* ADC12 Start Conversion */
#define ADC12ENC_L (0x0002u) /* ADC12 Enable Conversion */
#define ADC12TOVIE_L (0x0004u) /* ADC12 Timer Overflow interrupt enable */
#define ADC12OVIE_L (0x0008u) /* ADC12 Overflow interrupt enable */
#define ADC12ON_L (0x0010u) /* ADC12 On/enable */
#define ADC12REFON_L (0x0020u) /* ADC12 Reference on */
#define ADC12REF2_5V_L (0x0040u) /* ADC12 Ref 0:1.5V / 1:2.5V */
#define ADC12MSC_L (0x0080u) /* ADC12 Multiple SampleConversion */
/* ADC12CTL0 Control Bits */
#define ADC12SHT00_H (0x0001u) /* ADC12 Sample Hold 0 Select Bit: 0 */
#define ADC12SHT01_H (0x0002u) /* ADC12 Sample Hold 0 Select Bit: 1 */
#define ADC12SHT02_H (0x0004u) /* ADC12 Sample Hold 0 Select Bit: 2 */
#define ADC12SHT03_H (0x0008u) /* ADC12 Sample Hold 0 Select Bit: 3 */
#define ADC12SHT10_H (0x0010u) /* ADC12 Sample Hold 1 Select Bit: 0 */
#define ADC12SHT11_H (0x0020u) /* ADC12 Sample Hold 1 Select Bit: 1 */
#define ADC12SHT12_H (0x0040u) /* ADC12 Sample Hold 1 Select Bit: 2 */
#define ADC12SHT13_H (0x0080u) /* ADC12 Sample Hold 1 Select Bit: 3 */
#define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */
#define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */
#define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */
#define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */
#define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */
#define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */
#define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */
#define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */
#define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */
#define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */
#define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */
#define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */
#define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */
#define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */
#define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */
#define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */
#define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */
#define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */
#define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */
#define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */
#define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */
#define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */
#define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */
#define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */
#define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */
#define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */
#define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */
#define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */
#define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */
#define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */
#define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */
#define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */
/* ADC12CTL1 Control Bits */
#define ADC12BUSY (0x0001u) /* ADC12 Busy */
#define ADC12CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */
#define ADC12CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */
#define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select Bit: 0 */
#define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select Bit: 1 */
#define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */
#define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */
#define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */
#define ADC12ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */
#define ADC12SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */
#define ADC12SHS0 (0x0400u) /* ADC12 Sample/Hold Source Bit: 0 */
#define ADC12SHS1 (0x0800u) /* ADC12 Sample/Hold Source Bit: 1 */
#define ADC12CSTARTADD0 (0x1000u) /* ADC12 Conversion Start Address Bit: 0 */
#define ADC12CSTARTADD1 (0x2000u) /* ADC12 Conversion Start Address Bit: 1 */
#define ADC12CSTARTADD2 (0x4000u) /* ADC12 Conversion Start Address Bit: 2 */
#define ADC12CSTARTADD3 (0x8000u) /* ADC12 Conversion Start Address Bit: 3 */
/* ADC12CTL1 Control Bits */
#define ADC12BUSY_L (0x0001u) /* ADC12 Busy */
#define ADC12CONSEQ0_L (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */
#define ADC12CONSEQ1_L (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */
#define ADC12SSEL0_L (0x0008u) /* ADC12 Clock Source Select Bit: 0 */
#define ADC12SSEL1_L (0x0010u) /* ADC12 Clock Source Select Bit: 1 */
#define ADC12DIV0_L (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */
#define ADC12DIV1_L (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */
#define ADC12DIV2_L (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */
/* ADC12CTL1 Control Bits */
#define ADC12ISSH_H (0x0001u) /* ADC12 Invert Sample Hold Signal */
#define ADC12SHP_H (0x0002u) /* ADC12 Sample/Hold Pulse Mode */
#define ADC12SHS0_H (0x0004u) /* ADC12 Sample/Hold Source Bit: 0 */
#define ADC12SHS1_H (0x0008u) /* ADC12 Sample/Hold Source Bit: 1 */
#define ADC12CSTARTADD0_H (0x0010u) /* ADC12 Conversion Start Address Bit: 0 */
#define ADC12CSTARTADD1_H (0x0020u) /* ADC12 Conversion Start Address Bit: 1 */
#define ADC12CSTARTADD2_H (0x0040u) /* ADC12 Conversion Start Address Bit: 2 */
#define ADC12CSTARTADD3_H (0x0080u) /* ADC12 Conversion Start Address Bit: 3 */
#define ADC12CONSEQ_0 (0*2u) /* ADC12 Conversion Sequence Select: 0 */
#define ADC12CONSEQ_1 (1*2u) /* ADC12 Conversion Sequence Select: 1 */
#define ADC12CONSEQ_2 (2*2u) /* ADC12 Conversion Sequence Select: 2 */
#define ADC12CONSEQ_3 (3*2u) /* ADC12 Conversion Sequence Select: 3 */
#define ADC12SSEL_0 (0*8u) /* ADC12 Clock Source Select: 0 */
#define ADC12SSEL_1 (1*8u) /* ADC12 Clock Source Select: 1 */
#define ADC12SSEL_2 (2*8u) /* ADC12 Clock Source Select: 2 */
#define ADC12SSEL_3 (3*8u) /* ADC12 Clock Source Select: 3 */
#define ADC12DIV_0 (0*0x20u) /* ADC12 Clock Divider Select: 0 */
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