?? lcdh.txt
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#define DMA1TSEL_20 (20*0x0100u) /* DMA channel 1 transfer select 20: USCIA1 receive */
#define DMA1TSEL_21 (21*0x0100u) /* DMA channel 1 transfer select 21: USCIA1 transmit */
#define DMA1TSEL_22 (22*0x0100u) /* DMA channel 1 transfer select 22: USCIB1 receive */
#define DMA1TSEL_23 (23*0x0100u) /* DMA channel 1 transfer select 23: USCIB1 transmit */
#define DMA1TSEL_24 (24*0x0100u) /* DMA channel 1 transfer select 24: ADC12IFGx */
#define DMA1TSEL_25 (25*0x0100u) /* DMA channel 1 transfer select 25: Reserved */
#define DMA1TSEL_26 (26*0x0100u) /* DMA channel 1 transfer select 26: Reserved */
#define DMA1TSEL_27 (27*0x0100u) /* DMA channel 1 transfer select 27: Reserved */
#define DMA1TSEL_28 (28*0x0100u) /* DMA channel 1 transfer select 28: Reserved */
#define DMA1TSEL_29 (29*0x0100u) /* DMA channel 1 transfer select 29: Multiplier ready */
#define DMA1TSEL_30 (30*0x0100u) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
#define DMA1TSEL_31 (31*0x0100u) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
#define DMA2TSEL_0 (0*0x0001u) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
#define DMA2TSEL_1 (1*0x0001u) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */
#define DMA2TSEL_2 (2*0x0001u) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */
#define DMA2TSEL_3 (3*0x0001u) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */
#define DMA2TSEL_4 (4*0x0001u) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */
#define DMA2TSEL_5 (5*0x0001u) /* DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG) */
#define DMA2TSEL_6 (6*0x0001u) /* DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG) */
#define DMA2TSEL_7 (7*0x0001u) /* DMA channel 2 transfer select 7: Reserved */
#define DMA2TSEL_8 (8*0x0001u) /* DMA channel 2 transfer select 8: Reserved */
#define DMA2TSEL_9 (9*0x0001u) /* DMA channel 2 transfer select 9: Reserved */
#define DMA2TSEL_10 (10*0x0001u) /* DMA channel 2 transfer select 10: Reserved */
#define DMA2TSEL_11 (11*0x0001u) /* DMA channel 2 transfer select 11: Reserved */
#define DMA2TSEL_12 (12*0x0001u) /* DMA channel 2 transfer select 12: Reserved */
#define DMA2TSEL_13 (13*0x0001u) /* DMA channel 2 transfer select 13: Reserved */
#define DMA2TSEL_14 (14*0x0001u) /* DMA channel 2 transfer select 14: Reserved */
#define DMA2TSEL_15 (15*0x0001u) /* DMA channel 2 transfer select 15: Reserved */
#define DMA2TSEL_16 (16*0x0001u) /* DMA channel 2 transfer select 16: USCIA0 receive */
#define DMA2TSEL_17 (17*0x0001u) /* DMA channel 2 transfer select 17: USCIA0 transmit */
#define DMA2TSEL_18 (18*0x0001u) /* DMA channel 2 transfer select 18: USCIB0 receive */
#define DMA2TSEL_19 (19*0x0001u) /* DMA channel 2 transfer select 19: USCIB0 transmit */
#define DMA2TSEL_20 (20*0x0001u) /* DMA channel 2 transfer select 20: USCIA1 receive */
#define DMA2TSEL_21 (21*0x0001u) /* DMA channel 2 transfer select 21: USCIA1 transmit */
#define DMA2TSEL_22 (22*0x0001u) /* DMA channel 2 transfer select 22: USCIB1 receive */
#define DMA2TSEL_23 (23*0x0001u) /* DMA channel 2 transfer select 23: USCIB1 transmit */
#define DMA2TSEL_24 (24*0x0001u) /* DMA channel 2 transfer select 24: ADC12IFGx */
#define DMA2TSEL_25 (25*0x0001u) /* DMA channel 2 transfer select 25: Reserved */
#define DMA2TSEL_26 (26*0x0001u) /* DMA channel 2 transfer select 26: Reserved */
#define DMA2TSEL_27 (27*0x0001u) /* DMA channel 2 transfer select 27: Reserved */
#define DMA2TSEL_28 (28*0x0001u) /* DMA channel 2 transfer select 28: Reserved */
#define DMA2TSEL_29 (29*0x0001u) /* DMA channel 2 transfer select 29: Multiplier ready */
#define DMA2TSEL_30 (30*0x0001u) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
#define DMA2TSEL_31 (31*0x0001u) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
#define DMA0TSEL__DMA_REQ (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
#define DMA0TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */
#define DMA0TSEL__TA0CCR2 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */
#define DMA0TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */
#define DMA0TSEL__TA1CCR2 (4*0x0001u) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */
#define DMA0TSEL__TB0CCR0 (5*0x0001u) /* DMA channel 0 transfer select 5: TimerB (TB0CCR0.IFG) */
#define DMA0TSEL__TB0CCR2 (6*0x0001u) /* DMA channel 0 transfer select 6: TimerB (TB0CCR2.IFG) */
#define DMA0TSEL__RES7 (7*0x0001u) /* DMA channel 0 transfer select 7: Reserved */
#define DMA0TSEL__RES8 (8*0x0001u) /* DMA channel 0 transfer select 8: Reserved */
#define DMA0TSEL__RES9 (9*0x0001u) /* DMA channel 0 transfer select 9: Reserved */
#define DMA0TSEL__RES10 (10*0x0001u) /* DMA channel 0 transfer select 10: Reserved */
#define DMA0TSEL__RES11 (11*0x0001u) /* DMA channel 0 transfer select 11: Reserved */
#define DMA0TSEL__RES12 (12*0x0001u) /* DMA channel 0 transfer select 12: Reserved */
#define DMA0TSEL__RES13 (13*0x0001u) /* DMA channel 0 transfer select 13: Reserved */
#define DMA0TSEL__RES14 (14*0x0001u) /* DMA channel 0 transfer select 14: Reserved */
#define DMA0TSEL__RES15 (15*0x0001u) /* DMA channel 0 transfer select 15: Reserved */
#define DMA0TSEL__USCIA0RX (16*0x0001u) /* DMA channel 0 transfer select 16: USCIA0 receive */
#define DMA0TSEL__USCIA0TX (17*0x0001u) /* DMA channel 0 transfer select 17: USCIA0 transmit */
#define DMA0TSEL__USCIB0RX (18*0x0001u) /* DMA channel 0 transfer select 18: USCIB0 receive */
#define DMA0TSEL__USCIB0TX (19*0x0001u) /* DMA channel 0 transfer select 19: USCIB0 transmit */
#define DMA0TSEL__USCIA1RX (20*0x0001u) /* DMA channel 0 transfer select 20: USCIA1 receive */
#define DMA0TSEL__USCIA1TX (21*0x0001u) /* DMA channel 0 transfer select 21: USCIA1 transmit */
#define DMA0TSEL__USCIB1RX (22*0x0001u) /* DMA channel 0 transfer select 22: USCIB1 receive */
#define DMA0TSEL__USCIB1TX (23*0x0001u) /* DMA channel 0 transfer select 23: USCIB1 transmit */
#define DMA0TSEL__ADC12IFG (24*0x0001u) /* DMA channel 0 transfer select 24: ADC12IFGx */
#define DMA0TSEL__RES25 (25*0x0001u) /* DMA channel 0 transfer select 25: Reserved */
#define DMA0TSEL__RES26 (26*0x0001u) /* DMA channel 0 transfer select 26: Reserved */
#define DMA0TSEL__RES27 (27*0x0001u) /* DMA channel 0 transfer select 27: Reserved */
#define DMA0TSEL__RES28 (28*0x0001u) /* DMA channel 0 transfer select 28: Reserved */
#define DMA0TSEL__MPY (29*0x0001u) /* DMA channel 0 transfer select 29: Multiplier ready */
#define DMA0TSEL__DMA2IFG (30*0x0001u) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
#define DMA0TSEL__DMAE0 (31*0x0001u) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
#define DMA1TSEL__DMA_REQ (0*0x0100u) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
#define DMA1TSEL__TA0CCR0 (1*0x0100u) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */
#define DMA1TSEL__TA0CCR2 (2*0x0100u) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */
#define DMA1TSEL__TA1CCR0 (3*0x0100u) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */
#define DMA1TSEL__TA1CCR2 (4*0x0100u) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */
#define DMA1TSEL__TB0CCR0 (5*0x0100u) /* DMA channel 1 transfer select 5: TimerB (TB0CCR0.IFG) */
#define DMA1TSEL__TB0CCR2 (6*0x0100u) /* DMA channel 1 transfer select 6: TimerB (TB0CCR2.IFG) */
#define DMA1TSEL__RES7 (7*0x0100u) /* DMA channel 1 transfer select 7: Reserved */
#define DMA1TSEL__RES8 (8*0x0100u) /* DMA channel 1 transfer select 8: Reserved */
#define DMA1TSEL__RES9 (9*0x0100u) /* DMA channel 1 transfer select 9: Reserved */
#define DMA1TSEL__RES10 (10*0x0100u) /* DMA channel 1 transfer select 10: Reserved */
#define DMA1TSEL__RES11 (11*0x0100u) /* DMA channel 1 transfer select 11: Reserved */
#define DMA1TSEL__RES12 (12*0x0100u) /* DMA channel 1 transfer select 12: Reserved */
#define DMA1TSEL__RES13 (13*0x0100u) /* DMA channel 1 transfer select 13: Reserved */
#define DMA1TSEL__RES14 (14*0x0100u) /* DMA channel 1 transfer select 14: Reserved */
#define DMA1TSEL__RES15 (15*0x0100u) /* DMA channel 1 transfer select 15: Reserved */
#define DMA1TSEL__USCIA0RX (16*0x0100u) /* DMA channel 1 transfer select 16: USCIA0 receive */
#define DMA1TSEL__USCIA0TX (17*0x0100u) /* DMA channel 1 transfer select 17: USCIA0 transmit */
#define DMA1TSEL__USCIB0RX (18*0x0100u) /* DMA channel 1 transfer select 18: USCIB0 receive */
#define DMA1TSEL__USCIB0TX (19*0x0100u) /* DMA channel 1 transfer select 19: USCIB0 transmit */
#define DMA1TSEL__USCIA1RX (20*0x0100u) /* DMA channel 1 transfer select 20: USCIA1 receive */
#define DMA1TSEL__USCIA1TX (21*0x0100u) /* DMA channel 1 transfer select 21: USCIA1 transmit */
#define DMA1TSEL__USCIB1RX (22*0x0100u) /* DMA channel 1 transfer select 22: USCIB1 receive */
#define DMA1TSEL__USCIB1TX (23*0x0100u) /* DMA channel 1 transfer select 23: USCIB1 transmit */
#define DMA1TSEL__ADC12IFG (24*0x0100u) /* DMA channel 1 transfer select 24: ADC12IFGx */
#define DMA1TSEL__RES25 (25*0x0100u) /* DMA channel 1 transfer select 25: Reserved */
#define DMA1TSEL__RES26 (26*0x0100u) /* DMA channel 1 transfer select 26: Reserved */
#define DMA1TSEL__RES27 (27*0x0100u) /* DMA channel 1 transfer select 27: Reserved */
#define DMA1TSEL__RES28 (28*0x0100u) /* DMA channel 1 transfer select 28: Reserved */
#define DMA1TSEL__MPY (29*0x0100u) /* DMA channel 1 transfer select 29: Multiplier ready */
#define DMA1TSEL__DMA0IFG (30*0x0100u) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
#define DMA1TSEL__DMAE0 (31*0x0100u) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
#define DMA2TSEL__DMA_REQ (0*0x0001u) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
#define DMA2TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */
#define DMA2TSEL__TA0CCR2 (2*0x0001u) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */
#define DMA2TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */
#define DMA2TSEL__TA1CCR2 (4*0x0001u) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */
#define DMA2TSEL__TB0CCR0 (5*0x0001u) /* DMA channel 2 transfer select 5: TimerB (TB0CCR0.IFG) */
#define DMA2TSEL__TB0CCR2 (6*0x0001u) /* DMA channel 2 transfer select 6: TimerB (TB0CCR2.IFG) */
#define DMA2TSEL__RES7 (7*0x0001u) /* DMA channel 2 transfer select 7: Reserved */
#define DMA2TSEL__RES8 (8*0x0001u) /* DMA channel 2 transfer select 8: Reserved */
#define DMA2TSEL__RES9 (9*0x0001u) /* DMA channel 2 transfer select 9: Reserved */
#define DMA2TSEL__RES10 (10*0x0001u) /* DMA channel 2 transfer select 10: Reserved */
#define DMA2TSEL__RES11 (11*0x0001u) /* DMA channel 2 transfer select 11: Reserved */
#define DMA2TSEL__RES12 (12*0x0001u) /* DMA channel 2 transfer select 12: Reserved */
#define DMA2TSEL__RES13 (13*0x0001u) /* DMA channel 2 transfer select 13: Reserved */
#define DMA2TSEL__RES14 (14*0x0001u) /* DMA channel 2 transfer select 14: Reserved */
#define DMA2TSEL__RES15 (15*0x0001u) /* DMA channel 2 transfer select 15: Reserved */
#define DMA2TSEL__USCIA0RX (16*0x0001u) /* DMA channel 2 transfer select 16: USCIA0 receive */
#define DMA2TSEL__USCIA0TX (17*0x0001u) /* DMA channel 2 transfer select 17: USCIA0 transmit */
#define DMA2TSEL__USCIB0RX (18*0x0001u) /* DMA channel 2 transfer select 18: USCIB0 receive */
#define DMA2TSEL__USCIB0TX (19*0x0001u) /* DMA channel 2 transfer select 19: USCIB0 transmit */
#define DMA2TSEL__USCIA1RX (20*0x0001u) /* DMA channel 2 transfer select 20: USCIA1 receive */
#define DMA2TSEL__USCIA1TX (21*0x0001u) /* DMA channel 2 transfer select 21: USCIA1 transmit */
#define DMA2TSEL__USCIB1RX (22*0x0001u) /* DMA channel 2 transfer select 22: USCIB1 receive */
#define DMA2TSEL__USCIB1TX (23*0x0001u) /* DMA channel 2 transfer select 23: USCIB1 transmit */
#define DMA2TSEL__ADC12IFG (24*0x0001u) /* DMA channel 2 transfer select 24: ADC12IFGx */
#define DMA2TSEL__RES25 (25*0x0001u) /* DMA channel 2 transfer select 25: Reserved */
#define DMA2TSEL__RES26 (26*0x0001u) /* DMA channel 2 transfer select 26: Reserved */
#define DMA2TSEL__RES27 (27*0x0001u) /* DMA channel 2 transfer select 27: Reserved */
#define DMA2TSEL__RES28 (28*0x0001u) /* DMA channel 2 transfer select 28: Reserved */
#define DMA2TSEL__MPY (29*0x0001u) /* DMA channel 2 transfer select 29: Multiplier ready */
#define DMA2TSEL__DMA1IFG (30*0x0001u) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
#define DMA2TSEL__DMAE0 (31*0x0001u) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
/*************************************************************
* Flash Memory
*************************************************************/
#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
#define FCTL1_ (0x0140u) /* FLASH Control 1 */
DEFCW( FCTL1 , FCTL1_)
//sfrbw FCTL2 (0x0142) /* FLASH Control 2 */
#define FCTL3_ (0x0144u) /* FLASH Control 3 */
DEFCW( FCTL3 , FCTL3_)
#define FCTL4_ (0x0146u) /* FLASH Control 4 */
DEFCW( FCTL4 , FCTL4_)
#define FRPW (0x9600u) /* Flash password returned by read */
#define FWPW (0xA500u) /* Flash password for write */
#define FXPW (0x3300u) /* for use with XOR instruction */
#define FRKEY (0x9600u) /* (legacy definition) Flash key returned by read */
#define FWKEY (0xA500u) /* (legacy definition) Flash key for write */
#define FXKEY (0x3300u) /* (legacy definition) for use with XOR instruction */
/* FCTL1 Control Bits */
//#define RESERVED (0x0001u) /* Reserved */
#define ERASE (0x0002u) /* Enable bit for Flash segment erase */
#define MERAS (0x0004u) /* Enable bit for Flash mass erase */
//#define RESERVED (0x0008u) /* Reserved */
//#define RESERVED (0x0010u) /* Reserved */
#define SWRT (0x0020u) /* Smart Write enable */
#define WRT (0x0040u) /* Enable bit for Flash write */
#define BLKWRT (0x0080u) /* Enable bit for Flash segment write */
/* FCTL1 Control Bits */
//#define RESERVED (0x0001u) /* Reserved */
#define ERASE_L (0x0002u) /* Enable bit for Flash segment erase */
#define MERAS_L (0x0004u) /* Enable bit for Flash mass erase */
//#define RESERVED (0x0008u) /* Reserved */
//#define RESERVED (0x0010u) /* Reserved */
#define SWRT_L (0x0020u) /* Smart Write enable */
#define WRT_L (0x0040u) /* Enable bit for Flash write */
#define BLKWRT_L (0x0080u) /* Enable bit for Flash segment write */
/* FCTL1 Control Bits */
//#define RESERVED (0x0001u) /* Reserved */
//#define RESERVED (0x0008u) /* Reserved */
//#define RESERVED (0x0010u) /* Reserved */
/* FCTL3 Control Bits */
#define BUSY (0x0001u) /* Flash busy: 1 */
#define KEYV (0x0002u) /* Flash Key violation flag */
#define ACCVIFG (0x0004u) /* Flash Access violation flag */
#define WAIT (0x0008u) /* Wait flag for segment write */
#define LOCK (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX (0x0020u) /* Flash Emergency Exit */
#define LOCKA (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
//#define RESERVED (0x0080u) /* Reserved */
/* FCTL3 Control Bits */
#define BUSY_L (0x0001u) /* Flash busy: 1 */
#define KEYV_L (0x0002u) /* Flash Key violation flag */
#define ACCVIFG_L (0x0004u) /* Flash Access violation flag */
#define WAIT_L ?? 快捷鍵說明
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