?? adc4udrv.lst
字號:
151 AND #7FFFh
152 SACL C1_out
153
TMS320C24xx COFF Assembler Version 7.02 Sun Apr 27 20:34:16 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
adc4udrv.asm PAGE 4
154 LT C1_gain ;Ia_gain in Q13
155 MPY C1_out ;Q13 x Q15 = Q28
156 PAC
157 SACH C1_out,3 ;Convert final result to Q15
158
159 ;Read 2nd converted value
160 POINT_PF1
161 LACC ADC_FIFO2 ;
162
163 LDP #A4_ch_sel
164 SFR
165 AND #7FFFh
166 SACL C2_out
167 LT C2_gain ;Ib_gain in Q13
168 MPY C2_out ;Q13 x Q15 = Q28
169 PAC
170 SACH C2_out,3 ;Convert final result to Q15
171
172 ;Read 3rd converted value
173 POINT_PF1
174 LACC ADC_FIFO1
175
176 LDP #A4_ch_sel
177 SFR
178 AND #7FFFh
179 SACL C3_out
180 LT C3_gain ;Ia_gain in Q13
181 MPY C3_out ;Q13 x Q15 = Q28
182 PAC
183 SACH C3_out,3 ;Convert final result to Q15
184
185 ;Read 4th converted value
186 POINT_PF1
187 LACC ADC_FIFO2 ;
188
189 LDP #A4_ch_sel
190 SFR
191 AND #7FFFh
192 SACL C4_out
193 LT C4_gain ;Ib_gain in Q13
194 MPY C4_out ;Q13 x Q15 = Q28
195 PAC
196 SACH C4_out,3 ;Scale to Q15
197
198 CLRC SXM ;Sign extension mode off
199
200
201 ;Start another conversion
202 START_NXT:
203 LACC A4_ch_sel,1
204 AND #000Eh
205 SACL MASK
206 LACC A4_ch_sel
207 AND #0070h
TMS320C24xx COFF Assembler Version 7.02 Sun Apr 27 20:34:16 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
adc4udrv.asm PAGE 5
208 OR MASK
209 OR #1101100100000001b
210 ;5432109876543210
211
212 POINT_PF1
213 SACL ADC_CNTL1 ;Start 1st Dual conversion
214
215
216 LDP #A4_ch_sel
217 LACC A4_ch_sel,9
218 AND #000Eh,16
219 SACH MASK
220 LACC A4_ch_sel,8
221 AND #0070h,16
222 SACH GPR1adc
223 LACC GPR1adc
224 OR MASK
225 OR #1101100100000001b
226 ;5432109876543210
227
228 POINT_PF1
229 SACL ADC_CNTL1 ;Start 2nd Dual conversion
230
231
232 LDP #A4_ch_sel
233 RET
234
235 .endif
236 ;-----------------------------------
237
238 ;---target dependancy---------------
239 .if (x2407) ;target dependancy
240
241 ;Read 1st converted value
242 0016 bce1 LDP #ADCL_CNTL1>>7
243 0017 1028 LACC ADC_RESULT0
244 0018 be0a SFR
245 0019 bfb0 AND #7FFFh
001a 7fff
246 001b bc00- LDP #A4_ch_sel
247 001c 9004- SACL C1_out
248 001d 7300- LT C1_gain ;Ia_gain in Q13
249 001e 5404- MPY C1_out ;Q13 x Q15 = Q28
250 001f be03 PAC
251 0020 9b04- SACH C1_out,3 ;Convert final result to Q15
252
253 ;Read 2nd converted value
254 0021 bce1 LDP #ADCL_CNTL1>>7
255 0022 1029 LACC ADC_RESULT1
256 0023 be0a SFR
257 0024 bfb0 AND #7FFFh
0025 7fff
258 0026 bc00- LDP #A4_ch_sel
259 0027 9005- SACL C2_out
TMS320C24xx COFF Assembler Version 7.02 Sun Apr 27 20:34:16 2003
Copyright (c) 1987-2002 Texas Instruments Incorporated
adc4udrv.asm PAGE 6
260 0028 7301- LT C2_gain ;Ia_gain in Q13
261 0029 5405- MPY C2_out ;Q13 x Q15 = Q28
262 002a be03 PAC
263 002b 9b05- SACH C2_out,3 ;Convert final result to Q15
264
265 ;Read 3rd converted value
266 002c bce1 LDP #ADCL_CNTL1>>7
267 002d 102a LACC ADC_RESULT2
268 002e be0a SFR
269 002f bfb0 AND #7FFFh
0030 7fff
270 0031 bc00- LDP #A4_ch_sel
271 0032 9006- SACL C3_out
272 0033 7302- LT C3_gain ;Ia_gain in Q13
273 0034 5406- MPY C3_out ;Q13 x Q15 = Q28
274 0035 be03 PAC
275 0036 9b06- SACH C3_out,3 ;Convert final result to Q15
276
277 ;Read 4th converted value
278 0037 bce1 LDP #ADCL_CNTL1>>7
279 0038 102b LACC ADC_RESULT3
280 0039 be0a SFR
281 003a bfb0 AND #7FFFh
003b 7fff
282 003c bc00- LDP #A4_ch_sel
283 003d 9007- SACL C4_out
284 003e 7303- LT C4_gain ;Ia_gain in Q13
285 003f 5407- MPY C4_out ;Q13 x Q15 = Q28
286 0040 be03 PAC
287 0041 9b07- SACH C4_out,3 ;Convert final result to Q15
288
289 ;Start another conversion
290 0042 START_NXT:
291 0042 1008- LACC A4_ch_sel
292 0043 bce1 LDP #ADCL_CNTL1>>7
293 0044 9023 SACL CHSELSEQ1
294 0045 ae21 SPLK #0110000000000000b,ADCL_CNTL2 ;Reset + SOC SEQ1
0046 6000
295 ;||||!!!!||||!!!!
296 ;5432109876543210
297
298 0047 bc00- LDP #A4_ch_sel
299 0048 ef00 RET
300
301 .endif
302 ;-----------------------------------
No Errors, No Warnings
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