?? i2vd_drv.asm
字號:
;===========================================================================
; File Name: i2vd_drv.asm
;
; Module Name: ILEG2_DCBUS_DRV
;
; Initialization Routine: ILEG2_DCBUS_DRV_INIT
;
; Originator: Digital Control Systems Group
; Texas Instruments
;
; Description: Measure two line currents Ia and Ib. The line current Ic
; is calculated basing on the measured Ia and Ib. The DC-bus
; voltage Vdc in the inverter is also measured.
;
;
; |~~~~~~~~~~~~~~~~~~~~~~|
; Ch_sel o---------->| |
; Imeas_a_gain o---------->|Q13 |
; Imeas_b_gain o---------->|Q13 Q15|----->o Imeas_a
; Vdc_meas_gain o---------->|Q13 ILEG2_DCBUS_DRV Q15|----->o Imeas_b
; Imeas_a_offset o---------->|Q15 Q15|----->o Imeas_c
; Imeas_b_offset o---------->|Q15 Q15|----->o Vdc_meas
; Vdc_meas_offseto---------->|Q15 |
; |______________________|
;
; Notes: - The Ia and Ib are the bipolar signals (i.e., alternating signals)
; while the Vdc is the unipolar signal (i.e., direct signal).
; - The signals are converted to Q15 variables by means of
; * For Ia and Ib (bipolar case), XOR #8000h
; * For Vdc (unipolar case), SFR and AND #7FFFh
; - The raw ADC digitized data is 10-bit length but it is left
; justified in the 16-bit result register.
; - All ADC input signals are expected to be
; * For x24x, 0->5.0 volt
; * For x2407, 0->3.3 volt
;
; Configuration info:
; 1. Imeas_x_gain/Vdc_meas_gain has range of -3.999999 --> +3.99999 (i.e. Q13)
; 2. Imeas_x_offset/Vdc_meas_offset has range of -0.999999 --> +0.99999 (i.e. Q15)
; 3. Imeas_x/Vdc_meas has range of -0.999999 --> +0.99999 (i.e. Q15)
; with:
; 1.0 x (VrefHi - VrefLo) = +0.999999 (7FFFh)
; 0.5 x (VrefHi - VrefLo) = 0 (0000/FFFFh)
; 0.0 x (VrefHi - VrefLo) = -0.999999 (8000h)
;
; Ch_sel HEX values vs Channels selected configuration as below
; _______________________________________________________________________
; | Not used | Vdc_meas selected | Imeas_b selected | Imeas_a selected |
; -----------------------------------------------------------------------
; | 4 bit | 4 bit | 4 bit | 4 bit |
; -----------------------------------------------------------------------
;
; For x240
; Imeas_a/Vdc_meas select: 0,1,2...7 --> Ch0,1,2,...7
; Imeas_b select: 0,1,2...7 --> Ch8,9,10,...15
;
; For x243
; Imeas_x/Vdc_meas select: 0,1,2...7 --> Ch0,1,2,...7
;
; For x2407
; Imeas_x/Vdc_meas select: 0,1,2...F --> Ch0,1,2,...15
;
; Default channels are configured as shown below:
; Imeas_a Channel 2
; Imeas_b Channel 3
; Vdc_meas Channel 13
; Not used Channel 0
; Ch_sel = 0D32h [Not used|Vdc_meas|Imeas_b|Imeas_a]
;
; Note: the channel selection can be reconfigured at ILEG2_DCBUS_DRV_INIT
;
; Target dependency: C2xx core only
;
;
;=====================================================================================
; History:
;-------------------------------------------------------------------------------------
; 9-15-2000 Release Rev 1.0
; (Caution !!) This mudule is tested only on x2407 (x24x does not work yet).
;===========================================================================
;(To use this Module, copy this section to main system file)
; .ref ILEG2_DCBUS_DRV, ILEG2_DCBUS_DRV_INIT ;function call
; .ref Ch_sel, Imeas_a_gain, Imeas_b_gain, Vdc_meas_gain ;Inputs
; .ref Imeas_a_offset, Imeas_b_offset, Vdc_meas_offset ;Inputs
; .ref Imeas_a, Imeas_b, Imeas_c, Vdc_meas ;Outputs
;===========================================================================
;Module definitions for external reference.
.def ILEG2_DCBUS_DRV, ILEG2_DCBUS_DRV_INIT ;function call
.def Ch_sel, Imeas_a_gain, Imeas_b_gain, Vdc_meas_gain ;Inputs
.def Imeas_a_offset, Imeas_b_offset, Vdc_meas_offset ;Inputs
.def Imeas_a, Imeas_b, Imeas_c, Vdc_meas ;Outputs
;===========================================================================
;CH_SEL_ .set 0D32h ; for ch_sel (EVM2407)
CH_SEL_ .set 0710h ; for ch_sel (eZdsp2407)
.include x24x_app.h
Ch_sel .usect "i2vd_drv",1
Imeas_a_gain .usect "i2vd_drv",1
Imeas_b_gain .usect "i2vd_drv",1
Vdc_meas_gain .usect "i2vd_drv",1
Imeas_a_offset .usect "i2vd_drv",1
Imeas_b_offset .usect "i2vd_drv",1
Vdc_meas_offset .usect "i2vd_drv",1
Imeas_a .usect "i2vd_drv",1
Imeas_b .usect "i2vd_drv",1
Imeas_c .usect "i2vd_drv",1
Vdc_meas .usect "i2vd_drv",1
GPR0adc .usect "i2vd_drv",1
GPR1adc .usect "i2vd_drv",1
;=========================
ILEG2_DCBUS_DRV_INIT:
;=========================
LDP #Ch_sel
SPLK #CH_SEL_,Ch_sel ;three default channels to Ch 13,3,2
SPLK #1FFFh, Imeas_a_gain ;Init with gain of 1
SPLK #1FFFh, Imeas_b_gain ;Init with gain of 1
SPLK #1FFFh, Vdc_meas_gain ;Init with gain of 1
SPLK #0h, Imeas_a_offset ;Init with no offset
SPLK #0h, Imeas_b_offset ;Init with no offset
SPLK #0h, Vdc_meas_offset ;Init with no offset
LDP #GPTCON>>7 ; Set T1 underflow (EVA) as ADC trigger
LACC GPTCON
AND #0FE7Fh
OR #0080h
SACL GPTCON
;---target dependancy---------------
.if (x240|x243) ;target dependancy
LDP #Ch_sel
LACC Ch_sel,1
AND #000Eh
SACL GPR0adc
LACC Ch_sel
AND #0070h
OR GPR0adc
OR #1111100100000000b
;!!!!||||!!!!||||
;5432109876543210
LDP #ADC_CNTL1>>7
SACL ADC_CNTL1 ;Ch0 (Imeas_a) & Ch1 (Imeas_b)
; ADC_CNTL2 need to be checked with x243
LDP #ADC_CNTL2>>7
;5432109876543210
;!!!!||||!!!!||||
SPLK #0000000000000010b, ADC_CNTL2 ;
.endif
;-----------------------------------
;---target dependancy---------------
.if (x2407) ;target dependancy
LDP #CALIBRATION>>7
SPLK #0, CALIBRATION ;Zero the Cal reg.
SPLK #0100000000000000b,ADCL_CNTL1 ;Reset entire Module
; SPLK #0010000000010000b,ADCL_CNTL1 ;Acq = 2 x Clks (CPS=0)
SPLK #0010000100010000b,ADCL_CNTL1 ;Acq = 4 x Clks (CPS=0)
; SPLK #0010001000010000b,ADCL_CNTL1 ;Acq = 6 x Clks (CPS=0)
; SPLK #0010001100010000b,ADCL_CNTL1 ;Acq = 8 x Clks (CPS=0)
;||||!!!!||||!!!! ;Cascaded mode
;5432109876543210
; SPLK #0010000000000010b,ADCL_CNTL2 ;Allow Software to start conversion
SPLK #0000001100000010b,ADCL_CNTL2 ;Allow EVA to start conversion
;||||!!!!||||!!!!
;5432109876543210
SPLK #2, MAXCONV ;Setup for 3 conversions
BLDD #Ch_sel,CHSELSEQ1 ;Configure channel select
.endif
RET
;-----------------------------------
;=========================
ILEG2_DCBUS_DRV:
;=========================
;---target dependancy---------------
.if (x240|x243) ;target dependancy
SETC SXM ; Sign extension mode on
SETC OVM ; Set overflow mode
SPM 0 ; Reset product mode
LDP #ADC_CNTL1>>7
WAIT
BIT ADC_CNTL1,BIT7 ; Check ADCEOC bit
BCND WAIT,TC ;
;Read 1st converted value
;Read ADC1 (Imeas_a)
LACC ADC_FIFO1 ;Ch0 (default) is for Imeas_a (i.e. Phase U)
XOR #8000h ;Convert to Q15 (Bipolar signal)
LDP #Imeas_a
SACL Imeas_a
LT Imeas_a_gain ;Imeas_a_gain in Q13
MPY Imeas_a ;Q13 x Q15 = Q28
PAC
ADD Imeas_a_offset,13 ;add offset in Q28
NEG ;Positive direction, current flows to motor
SACH Imeas_a,3 ;convert final result to Q15
;Read 2nd converted value
;Read ADC2 (Imeas_b)
LDP #ADC_FIFO2>>7
LACC ADC_FIFO2 ;Ch1 (default) is for Imeas_b (i.e. Phase V)
XOR #8000h ;Convert to Q15 (Bipolar signal)
LDP #Imeas_b
SACL Imeas_b
LT Imeas_b_gain ;Imeas_b_gain in Q13
MPY Imeas_b ;Q13 x Q15 = Q28
PAC
ADD Imeas_b_offset,13 ;add offset in Q28
NEG ;Positive direction, current flows to motor
SACH Imeas_b,3 ;convert final result to Q15
;Calculate Imeas_c
LACC Imeas_a ;Calculated value for Imeas_c (i.e. Phase W)
ADD Imeas_b ;ACC = Imeas_a + Imeas_b
NEG ;ACC = - (Imeas_a + Imeas_b)
SACL Imeas_c ;Imeas_c = - (Imeas_a + Imeas_b)
CLRC SXM ; Sign extension mode off
;Read 3rd converted value
;Read ADC1 (Vdc_meas)
LDP #ADC_FIFO1>>7
LACC ADC_FIFO1 ;Ch2 (default) is for DC_bus voltage
SFR ;Q15 conversion for Vdc_meas (Unipolar signal)
LDP #Vdc_meas
SACL Vdc_meas
LT Vdc_meas_gain ;Vdc_meas_gain in Q13
MPY Vdc_meas ;Q13 x Q15 = Q28
PAC
ADD Vdc_meas_offset,13 ;add offset in Q28
SACH Vdc_meas,3 ;convert final result to Q15
; Reconfigure channel select (Imeas_a and Imeas_b)
START_NXT
LDP #Ch_sel
LACC Ch_sel,1
AND #000Eh
SACL GPR0adc
LACC Ch_sel
AND #0070h
OR GPR0adc
OR #1111100100000000b
;!!!!||||!!!!||||
;5432109876543210
LDP #ADC_CNTL1>>7
SACL ADC_CNTL1 ;Ch0 (Imeas_a) & Ch1 (Imeas_b)
; Reconfigure channel select (Vdc_meas only)
LDP #Ch_sel
LACC Ch_sel,9
AND #000Eh,16
SACL GPR0adc
LACC Ch_sel,8
AND #0070h,16
SACH GPR1adc
LACC GPR1adc
OR GPR0adc
OR #1111100100000000b
;!!!!||||!!!!||||
;5432109876543210
LDP #ADC_CNTL1>>7
SACL ADC_CNTL1 ;Ch2 (Vdc_meas) & Ch0 (not used here)
.endif
;-----------------------------------
;---target dependancy---------------
.if (x2407) ;target dependancy
SETC SXM ; Sign extension mode on
SETC OVM ; Set overflow mode
SPM 0 ; Reset product mode
LDP #ADCL_CNTL2>>7
WAIT
BIT ADCL_CNTL2,BIT12 ; Check SEQ_BSY bit
BCND WAIT,TC ;
;Read 1st converted value (Imeas_a)
LACC ADC_RESULT0 ;Ch0 (default) is for Imeas_a (i.e. Phase U)
XOR #8000h ;Convert to Q15 (Bipolar signal)
LDP #Imeas_a
SACL Imeas_a
LT Imeas_a_gain ;Imeas_a_gain in Q13
MPY Imeas_a ;Q13 x Q15 = Q28
PAC
ADD Imeas_a_offset,13 ;add offset in Q28
NEG ;Positive direction, current flows to motor
SACH Imeas_a,3 ;convert final result to Q15
;Read 2nd converted value (Imeas_b)
LDP #ADC_RESULT1>>7
LACC ADC_RESULT1 ;Ch1 (default) is for Imeas_b (i.e. Phase V)
XOR #8000h ;Convert to Q15 (Bipolar signal)
LDP #Imeas_b
SACL Imeas_b
LT Imeas_b_gain ;Imeas_a_gain in Q13
MPY Imeas_b ;Q13 x Q15 = Q28
PAC
ADD Imeas_b_offset,13 ;add offset in Q28
NEG ;Positive direction, current flows to motor
SACH Imeas_b,3 ;convert final result to Q15
;Calculate Imeas_c
LACC Imeas_a ;Calculated value for Imeas_c (i.e. Phase W)
ADD Imeas_b ;ACC = Imeas_a + Imeas_b
NEG ;ACC = - (Imeas_a + Imeas_b)
SACL Imeas_c ;Imeas_c = - (Imeas_a + Imeas_b)
;Read 3rd converted value (Vdc_meas)
LDP #ADC_RESULT2>>7
LACC ADC_RESULT2 ;Ch2 (default) is for DC_bus voltage
SFR ;Convert to Q15 (Unipolar signal)
AND #7FFFh ;Convert to Q15 (Unipolar signal)
LDP #Vdc_meas
SACL Vdc_meas
LT Vdc_meas_gain ;Vdc_meas_gain in Q13
MPY Vdc_meas ;Q13 x Q15 = Q28
PAC
ADD Vdc_meas_offset,13 ;add offset in Q28
SACH Vdc_meas,3 ;convert final result to Q15
; Reconfigure channel select
START_NXT
LDP #CHSELSEQ1>>7
BLDD #Ch_sel,CHSELSEQ1 ;Configure channel select
; SPLK #0010000000000010b,ADCL_CNTL2 ;Allow Software to start conversion
;||||!!!!||||!!!!
;5432109876543210
.endif
CLRC SXM
RET
;-----------------------------------
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