?? regs24x.h
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/* ==================================================================================
File name: regs24x.h
Originator: Digital Control Systems Group
Texas Instruments
Description: F24x register definitions.
=====================================================================================
History:
-------------------------------------------------------------------------------------
9-15-2000 Release Rev 1.0
---------------------------------------------------------------------------------- */
#ifndef __REGS24X_H__
#define __REGS24X_H__
/* C2xx core registers */
#define IMR *((volatile int *)0x0004) /* Interrupt Mask Register */
#define GREG *((volatile int *)0x0005) /* Global memory allocation Register */
#define IFR *((volatile int *)0x0006) /* Interrupt Flag Register */
/* System configuration and interrupt registers*/
#define SYSCR *((volatile int *)0x7018) /* System Module Control Register. X240 only. */
#define SYSSR *((volatile int *)0x701A) /* System Module Status Register. X240 only. */
#define SYSIVR *((volatile int *)0x701E) /* System Interrupt Vector Register. X240 only. */
#define SCSR *((volatile int *)0x7018) /* System Control & System Status Reg. X241/2/3 only. */
#define DIN *((volatile int *)0x701C) /* Device Identification Register. */
#define PIVR *((volatile int *)0x701E) /* Peripheral Interrupt Vector Reg. X241/2/3 only. */
#define PIRQR0 *((volatile int *)0x7010) /* Peripheral Interrupt Request Reg 0. X241/2/3 only. */
#define PIRQR1 *((volatile int *)0x7011) /* Peripheral Interrupt Request Reg 1. X241/2/3 only. */
/* PLL configuration registers*/
#define CKCR0 *((volatile int *)0x702a) /* PLL Clock Control Register 0. X240 only.*/
/* External interrupt configuration registers */
#define XINT1CR *((volatile int *)7070h) /* Int1 (type A) Control reg for X240 only. */
/* External interrupt 1 config reg for X241/2/3 only. */
#define NMICR *((volatile int *)0x7072) /* Non maskable Int (type A) Control reg. X240 only. */
#define XINT2CR240 *((volatile int *)0x7078) /* Int2 (type C) Control reg. X240 only. */
#define XINT2CR241 *((volatile int *)0x7071) /* External interrupt 2 config. X241/2/3 only. */
#define XINT3CR *((volatile int *)0x707A) /* Int3 (type C) Control reg. X240 only. */
/* Digital I/O registers */
#define OCRA *((volatile int *)0x7090) /* Output Control Reg A */
#define MCRA *((volatile int *)0x7090) /* Output Control Reg A */
#define OCRB *((volatile int *)0x7092) /* Output Control Reg B */
#define MCRB *((volatile int *)0x7092) /* Output Control Reg B */
#define ISRA *((volatile int *)0x7094) /*Input Status Reg A. X240 only */
#define ISRB *((volatile int *)0x7096) /*Input Status Reg B. X240 only */
#define PADATDIR *((volatile int *)0x7098) /* I/O port A Data & Direction reg. */
#define PBDATDIR *((volatile int *)0x709A) /* I/O port B Data & Direction reg. */
#define PCDATDIR *((volatile int *)0x709C) /* I/O port C Data & Direction reg. */
#define PDDATDIR *((volatile int *)0x709E) /* I/O port D Data & Direction reg. */
/* Watchdog (WD) registers
#define WDCNTR *((volatile int *)0x7023) /* WD Counter reg */
#define WDKEY *((volatile int *)0x7025) /* WD Key reg */
#define WDCR *((volatile int *)0x7029) /* WD Control reg */
/* Real Time Interrupt registers */
#define RTICNTR *((volatile int *)0x7021) /* RTI counter reg. X240 only. */
#define RTICR *((volatile int *)0x7027) /* RTI control reg. X240 only. */
/* ADC registers */
#define ADCTRL1 *((volatile int *)0x7032) /* ADC Control Reg1 */
#define ADC_CNTL1 *((volatile int *)0X7032) /* ADC CONTROL reg 1 */
#define ADCTRL2 *((volatile int *)0x7034) /* ADC Control Reg2 */
#define ADC_CNTL2 *((volatile int *)0X7034) /* ADC CONTROL reg 2 */
#define ADCFIFO1 *((volatile int *)0x7036) /* ADC DATA REG FIFO for ADC1 */
#define ADC_FIFO1 *((volatile int *)0X7036) /* ADC FIFO data reg 1*/
#define ADCFIFO2 *((volatile int *)0x7038) /* ADC DATA REG FIFO for ADC2 */
#define ADC_FIFO2 *((volatile int *)0X7038) /* ADC FIFO data reg 2*/
/* SPI registers */
#define SPICCR *((volatile int *)0x7040) /* SPI Config Control Reg */
#define SPICTL *((volatile int *)0x7041) /* SPI Operation Control Reg */
#define SPISTS *((volatile int *)0x7042) /* SPI Status Reg */
#define SPIBRR *((volatile int *)0x7044) /* SPI Baud rate control reg */
#define SPIRXEMU *((volatile int *)0x7046) /* SPI Emulation buffer reg */
#define SPIRXBUF *((volatile int *)0x7047) /* SPI Serial receive buffer reg */
#define SPITXBUF *((volatile int *)0x7048) /* SPI Serial transmit buffer reg */
#define SPIDAT *((volatile int *)0x7049) /* SPI Serial data reg */
#define SPIPC1 *((volatile int *)0x704D) /* SPI Port Control Register 1. X240 only. */
#define SPIPC2 *((volatile int *)0x704E) /* SPI Port Control Register 2. X240 only. */
#define SPIPRI *((volatile int *)0x704F) /* SPI Priority control reg */
/* SCI registers */
#define SCICCR *((volatile int *)0x7050) /* SCI Communication control reg */
#define SCICTL1 *((volatile int *)0x7051) /* SCI Control reg1 */
#define SCIHBAUD *((volatile int *)0x7052) /* SCI Baud Rate MSbyte reg */
#define SCILBAUD *((volatile int *)0x7053) /* SCI Baud Rate LSbyte reg */
#define SCICTL2 *((volatile int *)0x7054) /* SCI Control reg2 */
#define SCIRXST *((volatile int *)0x7055) /* SCI Receiver Status reg */
#define SCIRXEMU *((volatile int *)0x7056) /* SCI Emulation Data Buffer reg */
#define SCIRXBUF *((volatile int *)0x7057) /* SCI Receiver Data buffer reg */
#define SCITXBUF *((volatile int *)0x7059) /* SCI Transmit Data buffer reg */
#define SCIPC2 *((volatile int *)0x705E) /* SCI Port Control reg2 (X240 only) */
#define SCIPRI *((volatile int *)0x705F) /* SCI Priority control reg */
/* Event Manager (EV) registers */
#define GPTCON *((volatile int *)0x7400) /* GP Timer control register. */
#define T1CNT *((volatile int *)0x7401) /* GP Timer 1 counter register. */
#define T1CMPR *((volatile int *)0x7402) /* GP Timer 1 compare register. */
#define T1PR *((volatile int *)0x7403) /* GP Timer 1 period register. */
#define T1PER *((volatile int *)0x7403) /* GP Timer 1 period register. */
#define T1CON *((volatile int *)0x7404) /* GP Timer 1 control register. */
#define T2CNT *((volatile int *)0x7405) /* GP Timer 2 counter register. */
#define T2CMPR *((volatile int *)0x7406) /* GP Timer 2 compare register. */
#define T2PR *((volatile int *)0x7407) /* GP Timer 2 period register. */
#define T2PER *((volatile int *)0x7407) /* GP Timer 2 period register. */
#define T2CON *((volatile int *)0x7408) /* GP Timer 2 control register. */
#define T3CNT *((volatile int *)0x7409) /* GP Timer 3 counter register. X240 only. */
#define T3CMPR *((volatile int *)0x740A) /* GP Timer 3 compare register. X240 only. */
#define T3PR *((volatile int *)0x740B) /* GP Timer 3 period register. X240 only. */
#define T3PER *((volatile int *)0x740B) /* GP Timer 3 period register. X240 only. */
#define T3CON *((volatile int *)0x740C) /* GP Timer 3 control register. X240 only. */
#define COMCON *((volatile int *)0x7411) /* Compare control register. */
#define ACTR *((volatile int *)0x7413) /* Full compare action control register. */
#define SACTR *((volatile int *)0x7414) /* Simple compare action control register. */
#define DBTCON *((volatile int *)0x7415) /* Dead-band timer control register. */
#define CMPR1 *((volatile int *)0x7417) /* Full compare unit compare register1. */
#define CMPR2 *((volatile int *)0x7418) /* Full compare unit compare register2. */
#define CMPR3 *((volatile int *)0x7419) /* Full compare unit compare register3. */
#define SCMPR1 *((volatile int *)0x741A) /* Simple compare unit compare register1. X240 only. */
#define SCMPR2 *((volatile int *)0x741B) /* Simple compare unit compare register2. X240 only. */
#define SCMPR3 *((volatile int *)0x741C) /* Simple compare unit compare register3. X240 only. */
#define CAPCON *((volatile int *)0x7420) /* Capture control register. */
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