while(1)             /* Nothing running in the background at present */
        {

        } /* Main system background loop */

} /* End: main() */


void interrupt c_int03()
{
        asm("      CLRC     XF ");
        
        isr_ticker++;
        
/*---------------------------------------------------------------------------*/
#if     TARGET==F243
        EVIFRB=0x0ffff;            /* Clear all Group A EV interrupt flags    */

#elif   TARGET==F2407
        EVAIFRB=0x0ffff;          /* Clear all EV1 Group A EV interrupt flags*/
#endif/* #if TARGET */

        if (bldc.align_flag != FALSE ) {
            bldc.mod6.cntr = 0;
            pwm.cmtn_ptr_bd = 0;
            pwm.update(&pwm);


             /* Wait for a "while" */

            if (bldc.cmtn.v_timer < V_TIMER_THRESHOLD){
                   update_v_timer();
                   dac.update(&dac);
                   asm("      SETC     XF ");
                   return;
            }/* if (bldc.cmtn.v_timer < V_TIMER_THRESHOLD)*/

            bldc.align_flag = 0;
        }/*if (bldc.align_flag != FALSE ) */

#if (BUILDLEVEL==LEVEL1)
        BLDC_TI_Run(&bldc);

        pwm.cmtn_ptr_bd  = bldc.mod6.cntr; /* Input to PWM driver */

        pwm.update(&pwm);
#endif /* (BUILDLEVEL==LEVEL1) */

#if (BUILDLEVEL==LEVEL2)

        bldc.cmtn.va = adc.c1_out;
        bldc.cmtn.vb = adc.c2_out;
        bldc.cmtn.vc = adc.c3_out;

        BLDC_TI_Run(&bldc);

        pwm.cmtn_ptr_bd  = bldc.mod6.cntr;  /* Input to PWM driver */

        pwm.update(&pwm);
        adc.update(&adc);
#endif /* (BUILDLEVEL==LEVEL2) */


#if (BUILDLEVEL==LEVEL3)

        bldc.cmtn.va = adc.c1_out;
        bldc.cmtn.vb = adc.c2_out;
        bldc.cmtn.vc = adc.c3_out;

        BLDC_TI_Run(&bldc);

        pwm.cmtn_ptr_bd  = bldc.mod6.cntr; /* Input to PWM driver */


        pwm.update(&pwm);
        adc.update(&adc);



#endif /* (BUILDLEVEL==LEVEL3) */


#if (BUILDLEVEL==LEVEL4)


        bldc.cmtn.va = adc.c1_out;
        bldc.cmtn.vb = adc.c2_out;
        bldc.cmtn.vc = adc.c3_out;

        BLDC_TI_Run(&bldc);

        pwm.cmtn_ptr_bd  = bldc.mod6.cntr;  /* Input to PWM driver */
        pwm.d_func = bldc.rmp2.out;

        pwm.update(&pwm);
        adc.update(&adc);

#endif /* (BUILDLEVEL==LEVEL4) */

#if (BUILDLEVEL==LEVEL5)


        bldc.cmtn.va = adc.c1_out;
        bldc.cmtn.vb = adc.c2_out;
        bldc.cmtn.vc = adc.c3_out;

        bldc.pid2.fb_reg2  = adc.c4_out;

        BLDC_TI_Run(&bldc);

        if(FALSE == bldc.I_loop_flg)
            pwm.d_func = bldc.rmp2.out;
        else
            pwm.d_func = bldc.pid2.out_reg2;

        pwm.cmtn_ptr_bd = bldc.mod6.cntr;  /* Input to PWM driver */
        pwm.update(&pwm);
        adc.update(&adc);

#endif /* (BUILDLEVEL==LEVEL5) */

   update_v_timer();
   dac.update(&dac);

   asm("      SETC     XF ");


}  /* interrupt c_int03() */


void RstSystem(void)
{
/*-----------------------------------------------------------------------------
    First execute the initialization for the Wait Stage Genrator,
    Global interrupt disable, Shut off the Watchdog,
    and set up the Interupt Mask Register
-----------------------------------------------------------------------------*/
#if (TARGET==F243)
        disable_ints();           /* Make sure the interrupts are disabled   */
        IMR = 0x00;               /* Mask all interrupts                     */
        IFR = 0x00ff;             /* Clear any pending interrupts, if any    */
        PIRQR0 = PIRQR0 & 0x0fffe; /* Clear pending PDP flag */
        EVIFRA = EVIFRA | 0x0001;   /* Clear PDP int flag */

        asm("  CLRC   SXM ");         /* Clear signextension mode */
        asm("  CLRC   OVM ");         /* Reset overflow mode     */
        asm("  CLRC   CNF ");         /* Config block B0 to data memory */
        asm("  SPM    0   ");         /*  Set product mode at 0   */

        WSGR=WAIT_STATES;         /* Initialize Wait State Generator         */
        SCSR=0x40c0;              /* Init SCSR */
        wdog.disable();           /* Vccp/Wddis pin/bit must be high         */
        wdog.reset();             /* reset watchdog counter */

        EVIMRB=0x0004;        /* Enable the timer2 underflow interrupt */

        EVIFRA = 0xFFFF;      /* Clear all Group A interrupt flags */
        EVIFRB = 0xFFFF;      /* Clear all Group B interrupt flags */
        EVIFRC = 0xFFFF;      /* Clear all Group C interrupt flags */

        #if (REAL_TIME==TRUE)
        IMR = 0x0044;                /* En Int lvl 3 & 7 (T2 ISR) */
        #endif /* (REAL_TIME==TRUE) */

        #if (REAL_TIME==FALSE)
        IMR = 0x0004;                /* En Int lvl 3   (T2 ISR) */
        #endif /* (REAL_TIME==TRUE)*/

#endif /* (TARGET==F243) */

#if (TARGET==F2407)
        disable_ints();           /* Make sure the interrupts are disabled   */
        IMR = 0x00;               /* Mask all interrupts                     */
        IFR = 0x00ff;             /* Clear any pending interrupts, if any    */
        PIRQR0 = PIRQR0 & 0x0fffe; /* Clear pending PDP flag */
        PIRQR2 = PIRQR2 & 0x0fffe; /* Clear pending PDP flag */

        EVAIFRA = EVAIFRA | 0x0001; /* Clear PDPINTA flag */
        EVBIFRA = EVBIFRA | 0x0001; /* Clear PDPINTB flag */

        asm("  CLRC   SXM ");         /* Clear signextension mode */
        asm("  CLRC   OVM ");         /* Reset overflow mode     */
        asm("  CLRC   CNF ");         /* Config block B0 to data memory */
        asm("  SPM    0   ");         /*  Set product mode at 0   */

        WSGR=WAIT_STATES;         /* Initialize Wait State Generator */
        SCSR1=0x0085;             /* Init SCSR1 */
        wdog.disable();           /* Vccp/Wddis pin/bit must be high */
        wdog.reset();             /* reset watchdog counter */

        EVAIMRB=0x0004;        /* Enable the timer underflow interrupt */

        EVAIFRA = 0XFFFF;      /* Clear all Group A interrupt flags */
        EVAIFRB = 0XFFFF;      /* Clear all Group B interrupt flags */
        EVAIFRC = 0XFFFF;      /* Clear all Group C interrupt flags */

        #if (REAL_TIME==TRUE)
        IMR = 0X0044;                /* En Int lvl 3 & 7 (T2 ISR) */
        #endif /* (REAL_TIME==TRUE) */

        #if (REAL_TIME==FALSE)
        IMR = 0X0004;                /* En Int lvl 3   (T2 ISR) */
        #endif /* (REAL_TIME==TRUE)*/

#endif /* (TARGET==F2407) */

}   /* RstSystem(void) */


void interrupt phantom(void)
{

  static int phantom_count;
  phantom_count ++;


/*  Empty function: Used to handle any unwanted interrupts or events.
    All unused interrupt vectors are pointed to this function so that
    if any un-handled interrupts do get enabled, they are handled in a
    benign manner, preventing un-intended branches, calls or execution
    into garbage.
    Note that this function is an ISR, not a ordinary function.
*/
} /* phantom() */

/*------------------------------------------------------------------------------
    This function just provides a c-interface to the asm RTMON init function.
------------------------------------------------------------------------------*/

void rtmon_init(void)
{
    asm("       CALL    MON_RT_CNFG ");
}  /* rtmon_init() */


/*------------------------------------------------------------------------------
    This function derives time base from T2 underflow interrupt (i.e. period)
------------------------------------------------------------------------------*/

void time_base_init(void)
{
        T2PR = SYSTEM_INT_PERIOD;  /* Initialize period register */
/*
 * T2CON = 1001000001000000b
 * Operation is not affected by emulation suspend
 * Continuous up count mode
 * Enable timer operations
 */
        T2CON = 0x9040;

} /* time_base_init() */

void evm_pwm_init(void)
{
        MCRA     = MCRA & 0XBFFF;        /* Select Secondary function IOPB6 */
        PBDATDIR = PBDATDIR |0X4000;     /* Set IOPB6 as output        */
        PBDATDIR = PBDATDIR & EVM_IOPB6; /* Set IOPB6 low/high, Enable/disable PWM  */
} /* evm_pwm_init */

void update_v_timer(void)
{
   bldc.cmtn.v_timer++;                  /* Inc virtual timer */
   bldc.cmtn.v_timer = bldc.cmtn.v_timer & 0x7fff;   /* Force 15 bit wrap around and save */
}/* update_v_timer */