//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
-- Title      : Shift Register with synchronous reset
-- Project    : XUP Virtex-II Pro Demonstration System
-------------------------------------------------------------------------------
-- File       : sr2.v
-- Company    : Xilinx Inc
-- Created    : 2001/03/15
-- Last update: 2001/03/15
-- Copyright  : (c) Xilinx Inc 1999, 2000
-------------------------------------------------------------------------------
-- Uses       : 
-------------------------------------------------------------------------------
-- Used by    : onewire_master.v
-------------------------------------------------------------------------------

-- Description: Shift Register with synchronous reset
-------------------------------------------------------------------------------
*/

module SR2 (clk,reset,en,q);


input clk;	
input reset; 	// synchronous reset
input en;
output [7:0] q;

reg [7:0] q;

always @ (posedge clk) begin
	if (reset) begin
		q[7:0] <= 8'h01;
		end
	else if (en) begin
		q[7:1] <= q[6:0];
		q[0]	<= 1'b0;
		end
	end


endmodule