//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*
-------------------------------------------------------------------------------
-- Title      : defines
-- Project    : ML-XUP
-------------------------------------------------------------------------------
-- File       : defines.v
-- Company    : Xilinx, Inc.
-- Created    : 2001/03/15
-- Last Update: 2001/03/15
-- Copyright  : (c) Xilinx Inc, 2001
-------------------------------------------------------------------------------
-- Uses       : 
-------------------------------------------------------------------------------
-- Used by    : onewire_iface.v
-------------------------------------------------------------------------------
-- Description: This module defines the compile time options, the clock divider
--		    the presence of a pull up on the data line and if CRC checking is
--		    required.

set the CLK_DIV parameter based on the Input Clock Rate

  -----------------------------------------------------------
     Table : Generic Settings in Clock Divider Based on
             Input Clock Rates 
   -----------------------------------------------------------
   Min Input        Max Input     Divider   CLK_DIV 
   Clock Freq.     Clock Freq.     Ratio     Value
    (MHz)             (MHz) 
   -----------------------------------------------------------
      3              5                4         0
      5              9                8         1
      9             14                12        2
     14             18                16        3
     18             22                20        4
     22             26                24        5
     26             30                28        6
     30             34                32        7
     34             38                36        8
     38             42                40        9
     42             46                44        A
     46             50                48        B
     50             54                52        C
     54             58                56        D
     58             62                60        E
     62             80                64        F
   -----------------------------------------------------------
*/




`define CLK_DIV 7			// 27MHz clock input

`define CheckCRC			// enable CRC checking

//`define UsePULLUP		// use an EXTERNAL pullup resistor on the ONEWIRE DQ