//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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//     (c) Copyright 2004 Xilinx, Inc.
//     All rights reserved.
//
/*

-------------------------------------------------------------------------------
-- Title      : Ten bit Johnson counter with asynchronous reset
-- Project    : XUP Virtex-II Pro Demonstration System
-------------------------------------------------------------------------------
-- File       : jcnt2.v
-- Company    : Xilinx Inc
-- Created    : 2001/03/15
-- Last update: 2001/03/15
-- Copyright  : (c) Xilinx Inc 1999, 2000
-------------------------------------------------------------------------------
-- Uses       : 
-------------------------------------------------------------------------------
-- Used by    : onewire_master.v
-------------------------------------------------------------------------------

-- Description: Ten bit Johnson counter with asynchronous reset
-------------------------------------------------------------------------------
*/


module JCNT2 (clk,reset,en,q);
input clk;
input reset;
input en;
output [9:0] q;
reg [9:0] q;

always @ (posedge clk or posedge reset) begin
	if (reset) begin
		q[9:0] <= 10'h000;
		end
	else if (en) begin
		q[9:1] <= q[9:0];
		q[0]   <= !q[9];
		end
	end

endmodule