* 
* 
*2.4 kbps MELP Proposed Federal Standard speech coder
*
*TMS320C5x assembly code
*
*version 1.0
*
*Copyright (c) 1998, Texas Instruments, Inc.  
*
*Texas Instruments has intellectual property rights on the MELP
*algorithm.  The Texas Instruments contact for licensing issues for
*commercial and non-government use is William Gordon, Director,
*Government Contracts, Texas Instruments Incorporated, Semiconductor
*Group (phone 972 480 7442).

*
*************************************************************************
*
* The following code was hand optimized for the Texas Instuments
* TMS320C5x DSP by DSPCon, Inc.  For information, please contact DSPCon
* at:
* 
*                       DSPCon, Inc.
*                       380 Foothill Road
*                       Bridgewater, New Jersey 08807
*                       (908) 722-5656
*                       info@dspcon.com
*                       www.dspcon.com
*
*************************************************************************
	.if 0
/* VQ_ENC -
   encode vector with full VQ using unweighted Euclidean distance
    Synopsis: vq_enc(cb, u, levels, p, u_hat, indices)
	Input:
	    cb- one dimensional linear codebook array
	    u- dimension p, the parameters to be encoded (u[0  p-1])
	    levels- the number of levels
	    p- the predictor order
	Output:
	    u_hat-   the reconstruction vector (if non null)
	    a_indices- the codebook indices (for each stage) a_indices[0  stages-1]
	Parameters:
*/
/* Q values:
   cb - Q13
   u - Q13
   u_hat - Q13 */
	.endif

;  Code to perform tree search of a multi-stage VQ encoder

    .mmregs

    .def    _vq_enc


FP          .set    AR0
SP          .set    AR1
p_cb        .set    AR2
loopcnt     .set    AR3
u           .set    AR4
i           .set    AR5
tbufp       .set    AR6

;  Ram storage of page 4-7
PAGE6   .set    300h
INDICES .set    0
U_HAT   .set    1
P       .set    2
LEVELS  .set    3
U       .set    4
CB      .set    5

index   .set    8
zero    .set    9
d_low   .set    10
dmin_low  .set  11
d_high  .set    12
dmin_high .set  13
temp    .set    14
p_m1    .set    15
pram    .set    16
savAR6  .set    17

tmp_buf .set    20

    .text

; Save C context so that we may restore it upon exit
_vq_enc  .equ    $
    LDP     #6          ; Change the page pointer to on chip (fast ram)

; Take stack passed arguments and place them in fast direct RAM
    SBRK    6           ; Point SP to last argument
    RPT     #(6-1)      ; ARP assumed to be SP
      BLDD  *+,#(PAGE6+ INDICES)  ; Move all arguments to fast memory

; Save used C context registers
    SAR     AR6, savAR6

; Setup the C50 modes
    SSXM                ; enable sign extension
    SETC    OVM         ; enable saturation mode
    SPM     1


; init p_m1 to P -1
    LAC     P
    SUB     #1
    SACL    p_m1

    ZAC                 ; clear ACC for clearing
    SACL    index       ; index
    SACL    zero        ; zero
    SAMM    i           ; i

; init dmin to LW_MAX
    SPLK    #7fffh, dmin_high
    SPLK    #0ffffh, dmin_low

; init p_cb to cb
    LAR     p_cb, CB

; main outer loop
    LAC     LEVELS      ; init the AR outer loop count to levels -1
    SUB     #1
    SAMM    loopcnt
    LARP    u

; Set up circular addressing on U
    ZALS    U
    SAMM    CBSR1
    ADDS    p_m1
    SAMM    CBER1

; Set up circular addressing on tmp_buf
    LAC     #(PAGE6 + tmp_buf)
    SAMM    CBSR2
    ADDS    p_m1
    SAMM    CBER2


    LAC     #11101100b
    SAMM    CBCR

    LAR     u,U         ; init u pointer
    LAR     tbufp, #(PAGE6 + tmp_buf)

    ZALS    dmin_low    ; preload d_min for comparison
    ADDH    dmin_high
    SACB

    LAC     p_m1        ; load inner loop count
    SAMM    BRCR
oloop:

    RPTB    lend-1
	LAMM    p_cb
	TBLR    pram

	LAC     *+,0,p_cb
	SUB     pram
	MAR     *+,tbufp
	SACL    *+,0,u
lend:
    LARP    tbufp

    ZAP                 ; clear register d
    RPT     p_m1        ; now square and accumulate tmp_buf
	SQRA    *+      ;
    APAC                ; accumulate last product
    CRLT                ; compare d < d_min

    LARP    i
    XC      1, C
	SAR  i, index

    MAR     *+,loopcnt
    BANZD   oloop, *-, u
	LAC     p_m1    ; load inner loop count
	SAMM    BRCR


; Disable circular addressing
    ZAC
    SAMM    CBCR

    LARP    AR5         ; *indices = index
    LAR     AR5, INDICES
    LAC     index
    SACL    *

    SPM     0           ; u_hat <-- cb[p * index]
    LAC     CB
    LT      index
    MPY     P
    APAC
    SAMM    BMAR
    LAR     AR5, U_HAT
    RPT     p_m1
       BLPD    BMAR, *+

; Prepare to return to caller
exit:

; Restore used C context registers
    LAR     AR6, savAR6

    LACB                ; recall d_min
    RETD                ; return to caller with delay
       LARP    SP       ; Select ARP for "C" context re-entry
       CLRC    OVM      ; disable saturation mode
			; return occurs here
    .end