-------------------------------------------------------- CELL DFCN1Q -----library IEEE;use IEEE.STD_LOGIC_1164.all;-- synopsys translate_offlibrary IEEE;use IEEE.VITAL_Timing.all;-- synopsys translate_on-- entity declaration --entity DFCN1Q is-- synopsys translate_off   generic(      TimingChecksOn: Boolean := True;      InstancePath: STRING := "*";      Xon: Boolean := True;      MsgOn: Boolean := True;      tpd_CDN_Q                      :	VitalDelayType01 := (0.493 ns, 0.305 ns);      tpd_CP_Q                       :	VitalDelayType01 := (0.493 ns, 0.545 ns);      tsetup_D_CP_posedge_posedge    :  VitalDelayType := 0 ns;      tsetup_D_CP_negedge_posedge    :  VitalDelayType := 0 ns;      thold_D_CP_posedge_posedge    :  VitalDelayType := 0 ns;      thold_D_CP_negedge_posedge    :  VitalDelayType := 0 ns;      trecovery_CDN_CP_posedge_posedge    :  VitalDelayType := 0 ns;      thold_CDN_CP_posedge_posedge    :  VitalDelayType := 0 ns;--    tperiod_CP_posedge             :	VitalDelayType := 1.856 ns;      tpw_CP_posedge                 :	VitalDelayType := 0.842 ns;      tpw_CDN_posedge                :	VitalDelayType := 0.000 ns;      tpw_CP_negedge                 :	VitalDelayType := 1.014 ns;      tpw_CDN_negedge                :	VitalDelayType := 0.665 ns;      tipd_D                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_CP                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_CDN                       :	VitalDelayType01 := (0.000 ns, 0.000 ns));-- synopsys translate_on   port(      D                              :	in    STD_ULOGIC;      CP                             :	in    STD_ULOGIC;      CDN                            :	in    STD_ULOGIC;      Q                              :	out   STD_ULOGIC);attribute VITAL_LEVEL0 of DFCN1Q : entity is TRUE;end DFCN1Q;-- architecture body --library IEEE;use IEEE.VITAL_Primitives.all;library VITAL;use VITAL.VTABLES.all;architecture VITAL of DFCN1Q is   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;   SIGNAL D_ipd	 : STD_ULOGIC := 'X';   SIGNAL CP_ipd	 : STD_ULOGIC := 'X';   SIGNAL CDN_ipd	 : STD_ULOGIC := 'X';begin   ---------------------   --  INPUT PATH DELAYs   ---------------------   WireDelay : block   begin   VitalWireDelay (D_ipd, D, tipd_D);   VitalWireDelay (CP_ipd, CP, tipd_CP);   VitalWireDelay (CDN_ipd, CDN, tipd_CDN);   end block;   --------------------   --  BEHAVIOR SECTION   --------------------   VITALBehavior : process (D_ipd, CP_ipd, CDN_ipd)   -- timing check results   VARIABLE Tviol_D_CP_posedge	: STD_ULOGIC := '0';   VARIABLE Tmkr_D_CP_posedge	: VitalTimingDataType := VitalTimingDataInit;   VARIABLE Tviol_CDN_CP_posedge	: STD_ULOGIC := '0';   VARIABLE Tmkr_CDN_CP_posedge	: VitalTimingDataType := VitalTimingDataInit;   VARIABLE Pviol_CP	: STD_ULOGIC := '0';   VARIABLE PInfo_CP	: VitalPeriodDataType := VitalPeriodDataInit;   VARIABLE Pviol_CDN	: STD_ULOGIC := '0';   VARIABLE PInfo_CDN	: VitalPeriodDataType := VitalPeriodDataInit;   -- functionality results   VARIABLE Violation : STD_ULOGIC := '0';   VARIABLE PrevData_Q : STD_LOGIC_VECTOR(1 to 4);   VARIABLE D_delayed : STD_ULOGIC := 'X';   VARIABLE CP_delayed : STD_ULOGIC := 'X';   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');   ALIAS Q_zd : STD_LOGIC is Results(1);   -- output glitch detection variables   VARIABLE Q_GlitchData	: VitalGlitchDataType;   begin      ------------------------      --  Timing Check Section      ------------------------      if (TimingChecksOn) then         VitalSetupHoldCheck (          Violation               => Tviol_D_CP_posedge,          TimingData              => Tmkr_D_CP_posedge,          TestSignal              => D_ipd,          TestSignalName          => "D",          TestDelay               => 0 ns,          RefSignal               => CP_ipd,          RefSignalName          => "CP",          RefDelay                => 0 ns,          SetupHigh               => tsetup_D_CP_posedge_posedge,          SetupLow                => tsetup_D_CP_negedge_posedge,          HoldHigh               => thold_D_CP_posedge_posedge,          HoldLow                => thold_D_CP_negedge_posedge,          CheckEnabled            =>                            TO_X01((NOT CDN_ipd) ) /= '1',          RefTransition           => 'R',          HeaderMsg               => InstancePath & "/DFCN1Q",          Xon                     => Xon,          MsgOn                   => MsgOn,          MsgSeverity             => WARNING);         VitalRecoveryRemovalCheck (          Violation               => Tviol_CDN_CP_posedge,          TimingData              => Tmkr_CDN_CP_posedge,          TestSignal              => CDN_ipd,          TestSignalName          => "CDN",          TestDelay               => 0 ns,          RefSignal               => CP_ipd,          RefSignalName          => "CP",          RefDelay                => 0 ns,          Recovery                => trecovery_CDN_CP_posedge_posedge,          Removal                 => thold_CDN_CP_posedge_posedge,          ActiveLow               => TRUE,          CheckEnabled            =>                            TO_X01((NOT CDN_ipd) ) /= '1',          RefTransition           => 'R',          HeaderMsg               => InstancePath & "/DFCN1Q",          Xon                     => Xon,          MsgOn                   => MsgOn,          MsgSeverity             => WARNING);         VitalPeriodPulseCheck (          Violation               => Pviol_CP,          PeriodData              => PInfo_CP,          TestSignal              => CP_ipd,          TestSignalName          => "CP",          TestDelay               => 0 ns,--          Period                  => tperiod_CP_posedge,          PulseWidthHigh          => tpw_CP_posedge,          PulseWidthLow           => tpw_CP_negedge,          CheckEnabled            =>                            TO_X01((NOT CDN_ipd) ) /= '1',          HeaderMsg               => InstancePath &"/DFCN1Q",          Xon                     => Xon,          MsgOn                   => MsgOn,          MsgSeverity             => WARNING);         VitalPeriodPulseCheck (          Violation               => Pviol_CDN,          PeriodData              => PInfo_CDN,          TestSignal              => CDN_ipd,          TestSignalName          => "CDN",          TestDelay               => 0 ns,--          Period                  => 0 ns,          PulseWidthHigh          => tpw_CDN_posedge,          PulseWidthLow           => tpw_CDN_negedge,          CheckEnabled            =>                            TO_X01((NOT CDN_ipd) ) /= '1',          HeaderMsg               => InstancePath &"/DFCN1Q",          Xon                     => Xon,          MsgOn                   => MsgOn,          MsgSeverity             => WARNING);      end if;      -------------------------      --  Functionality Section      -------------------------      Violation := Tviol_D_CP_posedge or Tviol_CDN_CP_posedge or Pviol_CP or Pviol_CDN;      VitalStateTable(        Result => Q_zd,        PreviousDataIn => PrevData_Q,        StateTable => DFCN1_Q_tab,        DataIn => (               CDN_ipd, CP_delayed, D_delayed, CP_ipd));      Q_zd := Violation XOR Q_zd;      D_delayed := D_ipd;      CP_delayed := CP_ipd;      ----------------------      --  Path Delay Section      ----------------------      VitalPathDelay01 (       OutSignal => Q,       GlitchData => Q_GlitchData,       OutSignalName => "Q",       OutTemp => Q_zd,       Paths => (0 => (CDN_ipd'last_event, tpd_CDN_Q, TRUE),                 1 => (CP_ipd'last_event, tpd_CP_Q, TRUE)),       Mode => OnDetect,       Xon => Xon,       MsgOn => MsgOn,       MsgSeverity => WARNING);end process;end VITAL;configuration CFG_DFCN1Q_VITAL of DFCN1Q is   for VITAL   end for;end CFG_DFCN1Q_VITAL;-------------------------------------------------------- CELL HA1D1 -----library IEEE;use IEEE.STD_LOGIC_1164.all;-- synopsys translate_offlibrary IEEE;use IEEE.VITAL_Timing.all;-- synopsys translate_on-- entity declaration --entity HA1D1 is-- synopsys translate_off   generic(      TimingChecksOn: Boolean := True;      InstancePath: STRING := "*";      Xon: Boolean := True;      MsgOn: Boolean := True;      tpd_A_S                        :	VitalDelayType01 := (0.462 ns, 0.470 ns);      tpd_B_S                        :	VitalDelayType01 := (0.298 ns, 0.382 ns);      tpd_A_CO                       :	VitalDelayType01 := (0.288 ns, 0.393 ns);      tpd_B_CO                       :	VitalDelayType01 := (0.287 ns, 0.426 ns);      tipd_A                         :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_B                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));-- synopsys translate_on   port(      A                              :	in    STD_ULOGIC;      B                              :	in    STD_ULOGIC;      S                              :	out   STD_ULOGIC;      CO                             :	out   STD_ULOGIC);attribute VITAL_LEVEL0 of HA1D1 : entity is TRUE;end HA1D1;-- architecture body --library IEEE;use IEEE.VITAL_Primitives.all;library VITAL;use VITAL.VTABLES.all;architecture VITAL of HA1D1 is   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;   SIGNAL A_ipd	 : STD_ULOGIC := 'X';   SIGNAL B_ipd	 : STD_ULOGIC := 'X';begin   ---------------------   --  INPUT PATH DELAYs   ---------------------   WireDelay : block   begin   VitalWireDelay (A_ipd, A, tipd_A);   VitalWireDelay (B_ipd, B, tipd_B);   end block;   --------------------   --  BEHAVIOR SECTION   --------------------   VITALBehavior : process (A_ipd, B_ipd)   -- functionality results   VARIABLE Results : STD_LOGIC_VECTOR(1 to 2) := (others => 'X');   ALIAS S_zd : STD_LOGIC is Results(1);   ALIAS CO_zd : STD_LOGIC is Results(2);   -- output glitch detection variables   VARIABLE S_GlitchData	: VitalGlitchDataType;   VARIABLE CO_GlitchData	: VitalGlitchDataType;   begin      -------------------------      --  Functionality Section      -------------------------      S_zd := (B_ipd) XOR (A_ipd);      CO_zd := (B_ipd) AND (A_ipd);      ----------------------      --  Path Delay Section      ----------------------      VitalPathDelay01 (       OutSignal => S,       GlitchData => S_GlitchData,       OutSignalName => "S",       OutTemp => S_zd,       Paths => (0 => (A_ipd'last_event, tpd_A_S, TRUE),                 1 => (B_ipd'last_event, tpd_B_S, TRUE)),       Mode => OnDetect,       Xon => Xon,       MsgOn => MsgOn,       MsgSeverity => WARNING);      VitalPathDelay01 (       OutSignal => CO,       GlitchData => CO_GlitchData,       OutSignalName => "CO",       OutTemp => CO_zd,       Paths => (0 => (A_ipd'last_event, tpd_A_CO, TRUE),                 1 => (B_ipd'last_event, tpd_B_CO, TRUE)),       Mode => OnDetect,       Xon => Xon,       MsgOn => MsgOn,       MsgSeverity => WARNING);end process;end VITAL;configuration CFG_HA1D1_VITAL of HA1D1 is   for VITAL   end for;end CFG_HA1D1_VITAL;-------------------------------------------------------- CELL IND2D1 -----library IEEE;use IEEE.STD_LOGIC_1164.all;-- synopsys translate_offlibrary IEEE;use IEEE.VITAL_Timing.all;-- synopsys translate_on-- entity declaration --entity IND2D1 is-- synopsys translate_off   generic(      TimingChecksOn: Boolean := True;      InstancePath: STRING := "*";      Xon: Boolean := True;      MsgOn: Boolean := True;      tpd_A1_ZN                      :	VitalDelayType01 := (0.309 ns, 0.275 ns);      tpd_B1_ZN                      :	VitalDelayType01 := (0.166 ns, 0.139 ns);      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_B1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));-- synopsys translate_on   port(      A1                             :	in    STD_ULOGIC;      B1                             :	in    STD_ULOGIC;      ZN                             :	out   STD_ULOGIC);attribute VITAL_LEVEL0 of IND2D1 : entity is TRUE;end IND2D1;-- architecture body --library IEEE;use IEEE.VITAL_Primitives.all;library VITAL;use VITAL.VTABLES.all;architecture VITAL of IND2D1 is   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';   SIGNAL B1_ipd	 : STD_ULOGIC := 'X';begin   ---------------------   --  INPUT PATH DELAYs   ---------------------   WireDelay : block   begin   VitalWireDelay (A1_ipd, A1, tipd_A1);   VitalWireDelay (B1_ipd, B1, tipd_B1);   end block;   --------------------   --  BEHAVIOR SECTION   --------------------   VITALBehavior : process (A1_ipd, B1_ipd)   -- functionality results   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');   ALIAS ZN_zd : STD_LOGIC is Results(1);   -- output glitch detection variables   VARIABLE ZN_GlitchData	: VitalGlitchDataType;   begin      -------------------------      --  Functionality Section      -------------------------      ZN_zd := (NOT ((B1_ipd) AND ((NOT A1_ipd))));      ----------------------      --  Path Delay Section      ----------------------      VitalPathDelay01 (       OutSignal => ZN,       GlitchData => ZN_GlitchData,       OutSignalName => "ZN",       OutTemp => ZN_zd,       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),                 1 => (B1_ipd'last_event, tpd_B1_ZN, TRUE)),       Mode => OnDetect,       Xon => Xon,       MsgOn => MsgOn,       MsgSeverity => WARNING);end process;end VITAL;configuration CFG_IND2D1_VITAL of IND2D1 is   for VITAL   end for;end CFG_IND2D1_VITAL;-------------------------------------------------------- CELL INR2D0 -----library IEEE;use IEEE.STD_LOGIC_1164.all;-- synopsys translate_offlibrary IEEE;use IEEE.VITAL_Timing.all;-- synopsys translate_on-- entity declaration --entity INR2D0 is-- synopsys translate_off   generic(