TimingChecksOn: Boolean := True;      InstancePath: STRING := "*";      Xon: Boolean := True;      MsgOn: Boolean := True;      tpd_A1_ZN                      :	VitalDelayType01 := (0.237 ns, 0.250 ns);      tpd_B1_ZN                      :	VitalDelayType01 := (0.134 ns, 0.115 ns);      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_B1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));-- synopsys translate_on   port(      A1                             :	in    STD_ULOGIC;      B1                             :	in    STD_ULOGIC;      ZN                             :	out   STD_ULOGIC);attribute VITAL_LEVEL0 of INR2D0 : entity is TRUE;end INR2D0;-- architecture body --library IEEE;use IEEE.VITAL_Primitives.all;library VITAL;use VITAL.VTABLES.all;architecture VITAL of INR2D0 is   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';   SIGNAL B1_ipd	 : STD_ULOGIC := 'X';begin   ---------------------   --  INPUT PATH DELAYs   ---------------------   WireDelay : block   begin   VitalWireDelay (A1_ipd, A1, tipd_A1);   VitalWireDelay (B1_ipd, B1, tipd_B1);   end block;   --------------------   --  BEHAVIOR SECTION   --------------------   VITALBehavior : process (A1_ipd, B1_ipd)   -- functionality results   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');   ALIAS ZN_zd : STD_LOGIC is Results(1);   -- output glitch detection variables   VARIABLE ZN_GlitchData	: VitalGlitchDataType;   begin      -------------------------      --  Functionality Section      -------------------------      ZN_zd := (NOT ((B1_ipd) OR ((NOT A1_ipd))));      ----------------------      --  Path Delay Section      ----------------------      VitalPathDelay01 (       OutSignal => ZN,       GlitchData => ZN_GlitchData,       OutSignalName => "ZN",       OutTemp => ZN_zd,       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),                 1 => (B1_ipd'last_event, tpd_B1_ZN, TRUE)),       Mode => OnDetect,       Xon => Xon,       MsgOn => MsgOn,       MsgSeverity => WARNING);end process;end VITAL;configuration CFG_INR2D0_VITAL of INR2D0 is   for VITAL   end for;end CFG_INR2D0_VITAL;-------------------------------------------------------- CELL INV0 -----library IEEE;use IEEE.STD_LOGIC_1164.all;-- synopsys translate_offlibrary IEEE;use IEEE.VITAL_Timing.all;-- synopsys translate_on-- entity declaration --entity INV0 is-- synopsys translate_off   generic(      TimingChecksOn: Boolean := True;      InstancePath: STRING := "*";      Xon: Boolean := True;      MsgOn: Boolean := True;      tpd_I_ZN                       :	VitalDelayType01 := (0.121 ns, 0.102 ns);      tipd_I                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));-- synopsys translate_on   port(      I                              :	in    STD_ULOGIC;      ZN                             :	out   STD_ULOGIC);attribute VITAL_LEVEL0 of INV0 : entity is TRUE;end INV0;-- architecture body --library IEEE;use IEEE.VITAL_Primitives.all;library VITAL;use VITAL.VTABLES.all;architecture VITAL of INV0 is   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;   SIGNAL I_ipd	 : STD_ULOGIC := 'X';begin   ---------------------   --  INPUT PATH DELAYs   ---------------------   WireDelay : block   begin   VitalWireDelay (I_ipd, I, tipd_I);   end block;   --------------------   --  BEHAVIOR SECTION   --------------------   VITALBehavior : process (I_ipd)   -- functionality results   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');   ALIAS ZN_zd : STD_LOGIC is Results(1);   -- output glitch detection variables   VARIABLE ZN_GlitchData	: VitalGlitchDataType;   begin      -------------------------      --  Functionality Section      -------------------------      ZN_zd := (NOT I_ipd);      ----------------------      --  Path Delay Section      ----------------------      VitalPathDelay01 (       OutSignal => ZN,       GlitchData => ZN_GlitchData,       OutSignalName => "ZN",       OutTemp => ZN_zd,       Paths => (0 => (I_ipd'last_event, tpd_I_ZN, TRUE)),       Mode => OnDetect,       Xon => Xon,       MsgOn => MsgOn,       MsgSeverity => WARNING);end process;end VITAL;configuration CFG_INV0_VITAL of INV0 is   for VITAL   end for;end CFG_INV0_VITAL;-------------------------------------------------------- CELL MOAI22D0 -----library IEEE;use IEEE.STD_LOGIC_1164.all;-- synopsys translate_offlibrary IEEE;use IEEE.VITAL_Timing.all;-- synopsys translate_on-- entity declaration --entity MOAI22D0 is-- synopsys translate_off   generic(      TimingChecksOn: Boolean := True;      InstancePath: STRING := "*";      Xon: Boolean := True;      MsgOn: Boolean := True;      tpd_A1_ZN                      :	VitalDelayType01 := (0.161 ns, 0.121 ns);      tpd_A2_ZN                      :	VitalDelayType01 := (0.176 ns, 0.147 ns);      tpd_B1_ZN                      :	VitalDelayType01 := (0.257 ns, 0.226 ns);      tpd_B2_ZN                      :	VitalDelayType01 := (0.259 ns, 0.212 ns);      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_B1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_B2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));-- synopsys translate_on   port(      A1                             :	in    STD_ULOGIC;      A2                             :	in    STD_ULOGIC;      B1                             :	in    STD_ULOGIC;      B2                             :	in    STD_ULOGIC;      ZN                             :	out   STD_ULOGIC);attribute VITAL_LEVEL0 of MOAI22D0 : entity is TRUE;end MOAI22D0;-- architecture body --library IEEE;use IEEE.VITAL_Primitives.all;library VITAL;use VITAL.VTABLES.all;architecture VITAL of MOAI22D0 is   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';   SIGNAL B1_ipd	 : STD_ULOGIC := 'X';   SIGNAL B2_ipd	 : STD_ULOGIC := 'X';begin   ---------------------   --  INPUT PATH DELAYs   ---------------------   WireDelay : block   begin   VitalWireDelay (A1_ipd, A1, tipd_A1);   VitalWireDelay (A2_ipd, A2, tipd_A2);   VitalWireDelay (B1_ipd, B1, tipd_B1);   VitalWireDelay (B2_ipd, B2, tipd_B2);   end block;   --------------------   --  BEHAVIOR SECTION   --------------------   VITALBehavior : process (A1_ipd, A2_ipd, B1_ipd, B2_ipd)   -- functionality results   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');   ALIAS ZN_zd : STD_LOGIC is Results(1);   -- output glitch detection variables   VARIABLE ZN_GlitchData	: VitalGlitchDataType;   begin      -------------------------      --  Functionality Section      -------------------------      ZN_zd := ((B2_ipd) AND (B1_ipd)) OR ((NOT ((A2_ipd) OR (A1_ipd))));      ----------------------      --  Path Delay Section      ----------------------      VitalPathDelay01 (       OutSignal => ZN,       GlitchData => ZN_GlitchData,       OutSignalName => "ZN",       OutTemp => ZN_zd,       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),                 1 => (A2_ipd'last_event, tpd_A2_ZN, TRUE),                 2 => (B1_ipd'last_event, tpd_B1_ZN, TRUE),                 3 => (B2_ipd'last_event, tpd_B2_ZN, TRUE)),       Mode => OnDetect,       Xon => Xon,       MsgOn => MsgOn,       MsgSeverity => WARNING);end process;end VITAL;configuration CFG_MOAI22D0_VITAL of MOAI22D0 is   for VITAL   end for;end CFG_MOAI22D0_VITAL;-------------------------------------------------------- CELL MUX2D1 -----library IEEE;use IEEE.STD_LOGIC_1164.all;-- synopsys translate_offlibrary IEEE;use IEEE.VITAL_Timing.all;-- synopsys translate_on-- entity declaration --entity MUX2D1 is-- synopsys translate_off   generic(      TimingChecksOn: Boolean := True;      InstancePath: STRING := "*";      Xon: Boolean := True;      MsgOn: Boolean := True;      tpd_I0_Z                       :	VitalDelayType01 := (0.352 ns, 0.352 ns);      tpd_I1_Z                       :	VitalDelayType01 := (0.353 ns, 0.359 ns);      tpd_S_Z                        :	VitalDelayType01 := (0.360 ns, 0.323 ns);      tipd_I0                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_I1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_S                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));-- synopsys translate_on   port(      I0                             :	in    STD_ULOGIC;      I1                             :	in    STD_ULOGIC;      S                              :	in    STD_ULOGIC;      Z                              :	out   STD_ULOGIC);attribute VITAL_LEVEL0 of MUX2D1 : entity is TRUE;end MUX2D1;-- architecture body --library IEEE;use IEEE.VITAL_Primitives.all;library VITAL;use VITAL.VTABLES.all;architecture VITAL of MUX2D1 is   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;   SIGNAL I0_ipd	 : STD_ULOGIC := 'X';   SIGNAL I1_ipd	 : STD_ULOGIC := 'X';   SIGNAL S_ipd	 : STD_ULOGIC := 'X';begin   ---------------------   --  INPUT PATH DELAYs   ---------------------   WireDelay : block   begin   VitalWireDelay (I0_ipd, I0, tipd_I0);   VitalWireDelay (I1_ipd, I1, tipd_I1);   VitalWireDelay (S_ipd, S, tipd_S);   end block;   --------------------   --  BEHAVIOR SECTION   --------------------   VITALBehavior : process (I0_ipd, I1_ipd, S_ipd)   -- functionality results   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');   ALIAS Z_zd : STD_LOGIC is Results(1);   -- output glitch detection variables   VARIABLE Z_GlitchData	: VitalGlitchDataType;   begin      -------------------------      --  Functionality Section      -------------------------      Z_zd := VitalMUX                 (data => (I1_ipd, I0_ipd),                  dselect => (0 => S_ipd));      ----------------------      --  Path Delay Section      ----------------------      VitalPathDelay01 (       OutSignal => Z,       GlitchData => Z_GlitchData,       OutSignalName => "Z",       OutTemp => Z_zd,       Paths => (0 => (I0_ipd'last_event, tpd_I0_Z, TRUE),                 1 => (I1_ipd'last_event, tpd_I1_Z, TRUE),                 2 => (S_ipd'last_event, tpd_S_Z, TRUE)),       Mode => OnDetect,       Xon => Xon,       MsgOn => MsgOn,       MsgSeverity => WARNING);end process;end VITAL;configuration CFG_MUX2D1_VITAL of MUX2D1 is   for VITAL   end for;end CFG_MUX2D1_VITAL;-------------------------------------------------------- CELL ND2D0 -----library IEEE;use IEEE.STD_LOGIC_1164.all;-- synopsys translate_offlibrary IEEE;use IEEE.VITAL_Timing.all;-- synopsys translate_on-- entity declaration --entity ND2D0 is-- synopsys translate_off   generic(      TimingChecksOn: Boolean := True;      InstancePath: STRING := "*";      Xon: Boolean := True;      MsgOn: Boolean := True;      tpd_A1_ZN                      :	VitalDelayType01 := (0.144 ns, 0.123 ns);      tpd_A2_ZN                      :	VitalDelayType01 := (0.157 ns, 0.121 ns);      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));-- synopsys translate_on   port(      A1                             :	in    STD_ULOGIC;      A2                             :	in    STD_ULOGIC;      ZN                             :	out   STD_ULOGIC);attribute VITAL_LEVEL0 of ND2D0 : entity is TRUE;end ND2D0;-- architecture body --library IEEE;use IEEE.VITAL_Primitives.all;library VITAL;use VITAL.VTABLES.all;architecture VITAL of ND2D0 is   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';begin   ---------------------   --  INPUT PATH DELAYs   ---------------------   WireDelay : block   begin   VitalWireDelay (A1_ipd, A1, tipd_A1);