/* * * BRIEF MODULE DESCRIPTION *	Include file for Alchemy Semiconductor's Au1k CPU. * * Copyright 2000,2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. *         	ppopov@mvista.com or source@mvista.com * *  This program is free software; you can redistribute  it and/or modify it *  under  the terms of  the GNU General  Public License as published by the *  Free Software Foundation;  either version 2 of the  License, or (at your *  option) any later version. * *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT, *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * *  You should have received a copy of the  GNU General Public License along *  with this program; if not, write  to the Free Software Foundation, Inc., *  675 Mass Ave, Cambridge, MA 02139, USA. */ /*  * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp  */#ifndef _AU1X00_H_#define _AU1X00_H_#ifndef __ASSEMBLY__/* cpu pipeline flush */void static inline au_sync(void){	__asm__ volatile ("sync");}void static inline au_sync_udelay(int us){	__asm__ volatile ("sync");	udelay(us);}void static inline au_writeb(u8 val, int reg){	*(volatile u8 *)(reg) = val;}void static inline au_writew(u16 val, int reg){	*(volatile u16 *)(reg) = val;}void static inline au_writel(u32 val, int reg){	*(volatile u32 *)(reg) = val;}static inline u8 au_readb(unsigned long port){	return (*(volatile u8 *)port);}static inline u16 au_readw(unsigned long port){	return (*(volatile u16 *)port);}static inline u32 au_readl(unsigned long port){	return (*(volatile u32 *)port);}/* These next three functions should be a generic part of the MIPS * kernel (with the 'au_' removed from the name) and selected for * processors that support the instructions. * Taken from PPC tree.  -- Dan *//* Return the bit position of the most significant 1 bit in a word */static __inline__ int __ilog2(unsigned int x){	int lz;	asm volatile (		".set\tnoreorder\n\t"		".set\tnoat\n\t"		".set\tmips32\n\t"		"clz\t%0,%1\n\t"		".set\tmips0\n\t"		".set\tat\n\t"		".set\treorder"		: "=r" (lz)		: "r" (x));	return 31 - lz;}static __inline__ int au_ffz(unsigned int x){	if ((x = ~x) == 0)		return 32;	return __ilog2(x & -x);}/* * ffs: find first bit set. This is defined the same way as * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above ffz (man ffs). */static __inline__ int au_ffs(int x){	return __ilog2(x & -x) + 1;}#endif /* !ASSEMBLY */#ifdef CONFIG_PM/* no CP0 timer irq */#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)#else#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)#endif#define CP0_IWATCHLO		$18,1#define CP0_DEBUG		$23/* SDRAM Controller */#ifdef CONFIG_AU1550#define MEM_SDMODE0                0xB4000800#define MEM_SDMODE1                0xB4000808#define MEM_SDMODE2                0xB4000810#define MEM_SDADDR0                0xB4000820#define MEM_SDADDR1                0xB4000828#define MEM_SDADDR2                0xB4000830#define MEM_SDCONFIGA              0xB4000840#define MEM_SDCONFIGB              0xB4000848#define MEM_SDPRECMD               0xB40008c0#define MEM_SDAUTOREF              0xB40008c8#define MEM_SDWRMD0                0xB4000880#define MEM_SDWRMD1                0xB4000888#define MEM_SDWRMD2                0xB4000890#else /* CONFIG_AU1550 */#define MEM_SDMODE0                0xB4000000#define MEM_SDMODE1                0xB4000004#define MEM_SDMODE2                0xB4000008#define MEM_SDADDR0                0xB400000C#define MEM_SDADDR1                0xB4000010#define MEM_SDADDR2                0xB4000014#define MEM_SDREFCFG               0xB4000018#define MEM_SDPRECMD               0xB400001C#define MEM_SDAUTOREF              0xB4000020#define MEM_SDWRMD0                0xB4000024#define MEM_SDWRMD1                0xB4000028#define MEM_SDWRMD2                0xB400002C#endif /* CONFIG_AU1550 */#define MEM_SDSLEEP                0xB4000030#define MEM_SDSMCKE                0xB4000034/* Static Bus Controller */#define MEM_STCFG0                 0xB4001000#define MEM_STTIME0                0xB4001004#define MEM_STADDR0                0xB4001008#define MEM_STCFG1                 0xB4001010#define MEM_STTIME1                0xB4001014#define MEM_STADDR1                0xB4001018#define MEM_STCFG2                 0xB4001020#define MEM_STTIME2                0xB4001024#define MEM_STADDR2                0xB4001028#define MEM_STCFG3                 0xB4001030#define MEM_STTIME3                0xB4001034#define MEM_STADDR3                0xB4001038/* Interrupt Controller 0 */#define IC0_CFG0RD                 0xB0400040#define IC0_CFG0SET                0xB0400040#define IC0_CFG0CLR                0xB0400044#define IC0_CFG1RD                 0xB0400048#define IC0_CFG1SET                0xB0400048#define IC0_CFG1CLR                0xB040004C#define IC0_CFG2RD                 0xB0400050#define IC0_CFG2SET                0xB0400050#define IC0_CFG2CLR                0xB0400054#define IC0_REQ0INT                0xB0400054#define IC0_SRCRD                  0xB0400058#define IC0_SRCSET                 0xB0400058#define IC0_SRCCLR                 0xB040005C#define IC0_REQ1INT                0xB040005C#define IC0_ASSIGNRD               0xB0400060#define IC0_ASSIGNSET              0xB0400060#define IC0_ASSIGNCLR              0xB0400064#define IC0_WAKERD                 0xB0400068#define IC0_WAKESET                0xB0400068#define IC0_WAKECLR                0xB040006C#define IC0_MASKRD                 0xB0400070#define IC0_MASKSET                0xB0400070#define IC0_MASKCLR                0xB0400074#define IC0_RISINGRD               0xB0400078#define IC0_RISINGCLR              0xB0400078#define IC0_FALLINGRD              0xB040007C#define IC0_FALLINGCLR             0xB040007C#define IC0_TESTBIT                0xB0400080/* Interrupt Controller 1 */#define IC1_CFG0RD                 0xB1800040#define IC1_CFG0SET                0xB1800040#define IC1_CFG0CLR                0xB1800044#define IC1_CFG1RD                 0xB1800048#define IC1_CFG1SET                0xB1800048#define IC1_CFG1CLR                0xB180004C#define IC1_CFG2RD                 0xB1800050#define IC1_CFG2SET                0xB1800050#define IC1_CFG2CLR                0xB1800054#define IC1_REQ0INT                0xB1800054#define IC1_SRCRD                  0xB1800058#define IC1_SRCSET                 0xB1800058#define IC1_SRCCLR                 0xB180005C#define IC1_REQ1INT                0xB180005C#define IC1_ASSIGNRD               0xB1800060#define IC1_ASSIGNSET              0xB1800060#define IC1_ASSIGNCLR              0xB1800064#define IC1_WAKERD                 0xB1800068#define IC1_WAKESET                0xB1800068#define IC1_WAKECLR                0xB180006C#define IC1_MASKRD                 0xB1800070#define IC1_MASKSET                0xB1800070#define IC1_MASKCLR                0xB1800074#define IC1_RISINGRD               0xB1800078#define IC1_RISINGCLR              0xB1800078#define IC1_FALLINGRD              0xB180007C#define IC1_FALLINGCLR             0xB180007C#define IC1_TESTBIT                0xB1800080/* Interrupt Configuration Modes */#define INTC_INT_DISABLED                0#define INTC_INT_RISE_EDGE             0x1#define INTC_INT_FALL_EDGE             0x2#define INTC_INT_RISE_AND_FALL_EDGE    0x3#define INTC_INT_HIGH_LEVEL            0x5#define INTC_INT_LOW_LEVEL             0x6#define INTC_INT_HIGH_AND_LOW_LEVEL    0x7/* Interrupt Numbers */#define AU1X00_UART0_INT          0#define AU1000_UART1_INT          1 /* au1000 */#define AU1000_UART2_INT          2 /* au1000 */#define AU1500_PCI_INTA           1 /* au1500 */#define AU1500_PCI_INTB           2 /* au1500 */#define AU1X00_UART3_INT          3#define AU1000_SSI0_INT           4 /* au1000 */#define AU1000_SSI1_INT           5 /* au1000 */#define AU1500_PCI_INTC           4 /* au1500 */#define AU1500_PCI_INTD           5 /* au1500 */#define AU1X00_DMA_INT_BASE       6#define AU1X00_TOY_INT            14#define AU1X00_TOY_MATCH0_INT     15#define AU1X00_TOY_MATCH1_INT     16#define AU1X00_TOY_MATCH2_INT     17#define AU1X00_RTC_INT            18#define AU1X00_RTC_MATCH0_INT     19#define AU1X00_RTC_MATCH1_INT     20#define AU1X00_RTC_MATCH2_INT     21#define AU1000_IRDA_TX_INT        22 /* au1000 */#define AU1000_IRDA_RX_INT        23 /* au1000 */#define AU1X00_USB_DEV_REQ_INT    24#define AU1X00_USB_DEV_SUS_INT    25#define AU1X00_USB_HOST_INT       26#define AU1X00_ACSYNC_INT         27#define AU1X00_MAC0_DMA_INT       28#define AU1X00_MAC1_DMA_INT       29#define AU1X00_ETH0_IRQ           AU1X00_MAC0_DMA_INT#define AU1X00_ETH1_IRQ           AU1X00_MAC1_DMA_INT#define AU1000_I2S_UO_INT         30 /* au1000 */#define AU1X00_AC97C_INT          31#define AU1X00_LAST_INTC0_INT     AU1X00_AC97C_INT#define AU1X00_GPIO_0             32#define AU1X00_GPIO_1             33#define AU1X00_GPIO_2             34#define AU1X00_GPIO_3             35#define AU1X00_GPIO_4             36#define AU1X00_GPIO_5             37#define AU1X00_GPIO_6             38#define AU1X00_GPIO_7             39#define AU1X00_GPIO_8             40#define AU1X00_GPIO_9             41#define AU1X00_GPIO_10            42#define AU1X00_GPIO_11            43#define AU1X00_GPIO_12            44#define AU1X00_GPIO_13            45#define AU1X00_GPIO_14            46#define AU1X00_GPIO_15            47/* Au1000 only */#define AU1000_GPIO_16            48#define AU1000_GPIO_17            49#define AU1000_GPIO_18            50#define AU1000_GPIO_19            51#define AU1000_GPIO_20            52#define AU1000_GPIO_21            53#define AU1000_GPIO_22            54#define AU1000_GPIO_23            55#define AU1000_GPIO_24            56#define AU1000_GPIO_25            57#define AU1000_GPIO_26            58#define AU1000_GPIO_27            59#define AU1000_GPIO_28            60#define AU1000_GPIO_29            61#define AU1000_GPIO_30            62#define AU1000_GPIO_31            63/* Au1500 only */#define AU1500_GPIO_200           48#define AU1500_GPIO_201           49#define AU1500_GPIO_202           50#define AU1500_GPIO_203           51#define AU1500_GPIO_20            52#define AU1500_GPIO_204           53#define AU1500_GPIO_205           54#define AU1500_GPIO_23            55#define AU1500_GPIO_24            56#define AU1500_GPIO_25            57