/* * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> * * Configuation settings for the LART board. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef __CONFIG_H#define __CONFIG_H/* * High Level Configuration Options * (easy to change) */#define CONFIG_SA1100		1	/* This is an SA1100 CPU	*/#define CONFIG_LART		1	/* on an LART Board      */#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff *//* * Size of malloc() pool */#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data *//* * Hardware drivers */#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */#define CS8900_BASE		0x20008300#define CS8900_BUS16		1/* * select serial console configuration */#define CONFIG_SERIAL3          1	/* we use SERIAL 3 on LART *//* allow to overwrite serial and ethaddr */#define CONFIG_ENV_OVERWRITE#define CONFIG_BAUDRATE		9600#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#include <cmd_confdefs.h>#define CONFIG_BOOTDELAY	3#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600"#define CONFIG_ETHADDR		08:00:3e:26:0a:5b#define CONFIG_NETMASK          255.255.0.0#define CONFIG_IPADDR		172.22.2.131#define CONFIG_SERVERIP		172.22.2.126#define CONFIG_BOOTFILE		"elinos-lart"#define CONFIG_BOOTCOMMAND	"tftp; bootm"#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */#endif/* * Miscellaneous configurable options */#define	CFG_LONGHELP				/* undef to save memory		*/#define	CFG_PROMPT		"LART # "	/* Monitor Command Prompt	*/#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define	CFG_MAXARGS		16		/* max number of command args	*/#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */#define	CFG_LOAD_ADDR		0xc8000000	/* default load address	*/#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */#define CFG_CPUSPEED		0x0b		/* set core clock to 220 MHz */						/* valid baudrates */#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }/*----------------------------------------------------------------------- * Stack sizes * * The stack sizes are set up in start.S using the settings below */#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */#ifdef CONFIG_USE_IRQ#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */#endif/*----------------------------------------------------------------------- * Physical Memory Map */#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */#define PHYS_SDRAM_2		0xc1000000 /* SDRAM Bank #2 */#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */#define PHYS_SDRAM_3            0xc8000000 /* SDRAM Bank #3 */#define PHYS_SDRAM_3_SIZE       0x00800000 /* 8 MB */#define PHYS_SDRAM_4            0xc9000000 /* SDRAM Bank #4 */#define PHYS_SDRAM_4_SIZE       0x00800000 /* 8 MB */#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */#define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */#define CFG_FLASH_BASE		PHYS_FLASH_1/*----------------------------------------------------------------------- * FLASH and environment organization */#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/#define CFG_MAX_FLASH_SECT	(31+8)	/* max number of sectors on one chip	*//* timeout values are in ticks */#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */#define	CFG_ENV_IS_IN_FLASH	1#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/#endif	/* __CONFIG_H */