/* $Id$ */#ifndef _REGS_H#define _REGS_H/* Special Purpose Registers */#define SPR_CR		-1#define SPR_MSR		-2#define SPR_XER		1#define SPR_LR		8#define SPR_CTR		9#define SPR_DSISR	18#define SPR_DAR		19#define SPR_DEC		22#define SPR_SRR0	26#define SPR_SRR1	27#define SPR_EIE		80#define SPR_EID		81#define SPR_CMPA	144#define SPR_CMPB	145#define SPR_CMPC	146#define SPR_CMPD	147#define SPR_ICR		148#define SPR_DER		149#define SPR_COUNTA	150#define SPR_COUNTB	151#define SPR_CMPE	152#define SPR_CMPF	153#define SPR_CMPG	154#define SPR_CMPH	155#define SPR_LCTRL1	156#define SPR_LCTRL2	157#define SPR_ICTRL	158#define SPR_BAR		159#define SPR_USPRG0      256#define SPR_SPRG4_RO    260#define SPR_SPRG5_RO    261#define SPR_SPRG6_RO    262#define SPR_SPRG7_RO    263#define SPR_SPRG0	272#define SPR_SPRG1	273#define SPR_SPRG2	274#define SPR_SPRG3	275#define SPR_SPRG4       276#define SPR_SPRG5       277#define SPR_SPRG6       278#define SPR_SPRG7       279#define SPR_EAR         282	/* MPC603e core */#define SPR_TBL         284#define SPR_TBU         285#define SPR_PVR		287#define SPR_IC_CST	560#define SPR_IC_ADR	561#define SPR_IC_DAT	562#define SPR_DC_CST	568#define SPR_DC_ADR	569#define SPR_DC_DAT	570#define SPR_DPDR	630#define SPR_IMMR	638#define SPR_MI_CTR	784#define SPR_MI_AP	786#define SPR_MI_EPN	787#define SPR_MI_TWC	789#define SPR_MI_RPN	790#define SPR_MD_CTR	792#define SPR_M_CASID	793#define SPR_MD_AP	794#define SPR_MD_EPN	795#define SPR_M_TWB	796#define SPR_MD_TWC	797#define SPR_MD_RPN	798#define SPR_M_TW	799#define SPR_MI_DBCAM	816#define SPR_MI_DBRAM0	817#define SPR_MI_DBRAM1	818#define SPR_MD_DBCAM	824#define SPR_MD_DBRAM0	825#define SPR_MD_DBRAM1	826#define SPR_ZPR         944#define SPR_PID         945#define SPR_CCR0        947#define SPR_IAC3        948#define SPR_IAC4        949#define SPR_DVC1        950#define SPR_DVC2        951#define SPR_SGR         953#define SPR_DCWR        954#define SPR_SLER        955#define SPR_SU0R        956#define SPR_DBCR1       957#define SPR_ICDBDR      979#define SPR_ESR         980#define SPR_DEAR        981#define SPR_EVPR        982#define SPR_TSR         984#define SPR_TCR         986#define SPR_PIT         987#define SPR_SRR2        990#define SPR_SRR3        991#define SPR_DBSR        1008#define SPR_DBCR0       1010#define SPR_IABR        1010	/* MPC603e core */#define SPR_IAC1        1012#define SPR_IAC2        1013#define SPR_DAC1        1014#define SPR_DAC2        1015#define SPR_DCCR        1018#define SPR_ICCR        1019/* Bits for the DBCR0 register */#define DBCR0_EDM	0x80000000#define DBCR0_IDM	0x40000000#define DBCR0_RST	0x30000000#define DBCR0_IC	0x08000000#define DBCR0_BT	0x04000000#define DBCR0_EDE	0x02000000#define DBCR0_TDE	0x01000000#define DBCR0_IA1	0x00800000#define DBCR0_IA2	0x00400000#define DBCR0_IA12	0x00200000#define DBCR0_IA12X	0x00100000#define DBCR0_IA3	0x00080000#define DBCR0_IA4	0x00040000#define DBCR0_IA34	0x00020000#define DBCR0_IA34X	0x00010000#define DBCR0_IA12T	0x00008000#define DBCR0_IA34T	0x00004000#define DBCR0_FT	0x00000001/* Bits for the DBCR1 register */#define DBCR1_D1R	0x80000000#define DBCR1_D2R	0x40000000#define DBCR1_D1W	0x20000000#define DBCR1_D2W	0x10000000#define DBCR1_D1S	0x0C000000#define DBCR1_D2S	0x03000000#define DBCR1_DA12	0x00800000#define DBCR1_DA12X	0x00400000#define DBCR1_DV1M	0x000C0000#define DBCR1_DV2M	0x00030000#define DBCR1_DV1BE	0x0000F000#define DBCR1_DV2BE	0x00000F00/* Bits for the DBSR register */#define DBSR_IC		0x80000000#define DBSR_BT		0x40000000#define DBSR_EDE	0x20000000#define DBSR_TIE	0x10000000#define DBSR_UDE	0x08000000#define DBSR_IA1	0x04000000#define DBSR_IA2	0x02000000#define DBSR_DR1	0x01000000#define DBSR_DW1	0x00800000#define DBSR_DR2	0x00400000#define DBSR_DW2	0x00200000#define DBSR_IDE	0x00100000#define DBSR_IA3	0x00080000#define DBSR_IA4	0x00040000#define DBSR_MRR	0x00000300struct spr_info {  int  spr_val;  char spr_name[ 10 ];};extern struct spr_info spr_map[];extern const unsigned int n_sprs;#define SET_REGISTER( str, val ) \({ unsigned long __value = (val); \  asm volatile( str : : "r" (__value)); \  __value; })#define	GET_REGISTER( str ) \({ unsigned long __value; \  asm volatile( str : "=r" (__value) : ); \  __value; })#define	 GET_CR()	     GET_REGISTER( "mfcr %0" )#define	 SET_CR(val)	     SET_REGISTER( "mtcr %0", val )#define	 GET_MSR()	     GET_REGISTER( "mfmsr %0" )#define	 SET_MSR(val)	     SET_REGISTER( "mtmsr %0", val )#define	 GET_XER()	     GET_REGISTER( "mfspr %0,1" )#define	 SET_XER(val)	     SET_REGISTER( "mtspr 1,%0", val )#define	 GET_LR()	     GET_REGISTER( "mfspr %0,8" )#define	 SET_LR(val)	     SET_REGISTER( "mtspr 8,%0", val )#define	 GET_CTR()	     GET_REGISTER( "mfspr %0,9" )#define	 SET_CTR(val)	     SET_REGISTER( "mtspr 9,%0", val )#define	 GET_DSISR()	     GET_REGISTER( "mfspr %0,18" )#define	 SET_DSISR(val)	     SET_REGISTER( "mtspr 18,%0", val )#define	 GET_DAR()	     GET_REGISTER( "mfspr %0,19" )#define	 SET_DAR(val)	     SET_REGISTER( "mtspr 19,%0", val )#define	 GET_DEC()	     GET_REGISTER( "mfspr %0,22" )#define	 SET_DEC(val)	     SET_REGISTER( "mtspr 22,%0", val )#define	 GET_SRR0()	     GET_REGISTER( "mfspr %0,26" )#define	 SET_SRR0(val)       SET_REGISTER( "mtspr 26,%0", val )#define	 GET_SRR1()	     GET_REGISTER( "mfspr %0,27" )#define	 SET_SRR1(val)	     SET_REGISTER( "mtspr 27,%0", val )#define	 GET_EIE()	     GET_REGISTER( "mfspr %0,80" )