return 0;	return (high + 1 - low) << 20;}/********************************************************************* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.** Inputs: base and size of PCI SCS*********************************************************************/void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,		       unsigned int pciDramBase, unsigned int pciDramSize){	pciDramBase = pciDramBase & 0xfffff000;	pciDramBase = pciDramBase | (pciReadConfigReg (host,						       PCI_SCS_0_BASE_ADDRESS						       + 4 * bank,						       SELF) & 0x00000fff);	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF,			   pciDramBase);	if (pciDramSize == 0)		pciDramSize++;	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);}/********************************************************************* pciSetRegionFeatures - This function modifys one of the 8 regions with*                         feature bits given as an input.*                       - Be advised to check the spec before modifying them.* Inputs: PCI_PROTECT_REGION region - one of the eight regions.*         unsigned int features - See file: pci.h there are defintion for those*                                 region features.*         unsigned int baseAddress - The region base Address.*         unsigned int topAddress - The region top Address.* Returns: false if one of the parameters is erroneous true otherwise.*********************************************************************/bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,			   unsigned int features, unsigned int baseAddress,			   unsigned int regionLength){	unsigned int accessLow;	unsigned int accessHigh;	unsigned int accessTop = baseAddress + regionLength;	if (regionLength == 0) {	/* close the region. */		pciDisableAccessRegion (host, region);		return true;	}	/* base Address is store is bits [11:0] */	accessLow = (baseAddress & 0xfff00000) >> 20;	/* All the features are update according to the defines in pci.h (to be on	   the safe side we disable bits: [11:0] */	accessLow = accessLow | (features & 0xfffff000);	/* write to the Low Access Region register */	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,		      accessLow);	accessHigh = (accessTop & 0xfff00000) >> 20;	/* write to the High Access Region register */	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,		      accessHigh - 1);	return true;}/********************************************************************* pciDisableAccessRegion - Disable The given Region by writing MAX size*                           to its low Address and MIN size to its high Address.** Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.* Returns:  N/A.*********************************************************************/void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region){	/* writing back the registers default values. */	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,		      0x01001fff);	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);}/********************************************************************* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.** Inputs:   N/A* Returns:  true.*********************************************************************/bool pciArbiterEnable (PCI_HOST host){	unsigned int regData;	GT_REG_READ (pci_arbiter_control[host], &regData);	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);	return true;}/********************************************************************* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.** Inputs:   N/A* Returns:  true*********************************************************************/bool pciArbiterDisable (PCI_HOST host){	unsigned int regData;	GT_REG_READ (pci_arbiter_control[host], &regData);	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);	return true;}/********************************************************************* pciParkingDisable - Park on last option disable, with this function you can*                      disable the park on last mechanism for each agent.*                      disabling this option for all agents results parking*                      on the internal master.** Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.* Returns:  true*********************************************************************/bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,			PCI_AGENT_PARK externalAgent0,			PCI_AGENT_PARK externalAgent1,			PCI_AGENT_PARK externalAgent2,			PCI_AGENT_PARK externalAgent3,			PCI_AGENT_PARK externalAgent4,			PCI_AGENT_PARK externalAgent5){	unsigned int regData;	unsigned int writeData;	GT_REG_READ (pci_arbiter_control[host], &regData);	writeData = (internalAgent << 14) + (externalAgent0 << 15) +		(externalAgent1 << 16) + (externalAgent2 << 17) +		(externalAgent3 << 18) + (externalAgent4 << 19) +		(externalAgent5 << 20);	regData = (regData & ~(0x7f << 14)) | writeData;	GT_REG_WRITE (pci_arbiter_control[host], regData);	return true;}/********************************************************************* pciSetRegionSnoopMode - This function modifys one of the 4 regions which*                          supports Cache Coherency in the PCI_n interface.* Inputs: region - One of the four regions.*         snoopType - There is four optional Types:*                        1. No Snoop.*                        2. Snoop to WT region.*                        3. Snoop to WB region.*                        4. Snoop & Invalidate to WB region.*         baseAddress - Base Address of this region.*         regionLength - Region length.* Returns: false if one of the parameters is wrong otherwise return true.*********************************************************************/bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,			    PCI_SNOOP_TYPE snoopType,			    unsigned int baseAddress,			    unsigned int regionLength){	unsigned int snoopXbaseAddress;	unsigned int snoopXtopAddress;	unsigned int data;	unsigned int snoopHigh = baseAddress + regionLength;	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))		return false;	snoopXbaseAddress =		pci_snoop_control_base_0_low[host] + 0x10 * region;	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;	if (regionLength == 0) {	/* closing the region */		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);		GT_REG_WRITE (snoopXtopAddress, 0);		return true;	}	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */	data = (baseAddress >> 20) | snoopType << 12;	GT_REG_WRITE (snoopXbaseAddress, data);	snoopHigh = (snoopHigh & 0xfff00000) >> 20;	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);	return true;}/* * */static int gt_read_config_dword (struct pci_controller *hose,				 pci_dev_t dev, int offset, u32 * value){	int bus = PCI_BUS (dev);	if ((bus == local_buses[0]) || (bus == local_buses[1])) {		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,					   PCI_DEV (dev));	} else {		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->						     cfg_addr, offset,						     PCI_DEV (dev), bus);	}	return 0;}static int gt_write_config_dword (struct pci_controller *hose,				  pci_dev_t dev, int offset, u32 value){	int bus = PCI_BUS (dev);	if ((bus == local_buses[0]) || (bus == local_buses[1])) {		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,				   PCI_DEV (dev), value);	} else {		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,					     offset, PCI_DEV (dev), value,					     bus);	}	return 0;}/* * */static void gt_setup_ide (struct pci_controller *hose,			  pci_dev_t dev, struct pci_config_table *entry){	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };	u32 bar_response, bar_value;	int bar;	for (bar = 0; bar < 6; bar++) {		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,					0x0);		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,				       &bar_response);		pciauto_region_allocate (bar_response &					 PCI_BASE_ADDRESS_SPACE_IO ? hose->					 pci_io : hose->pci_mem, ide_bar[bar],					 &bar_value);		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,					bar_value);	}}#ifndef CONFIG_P3G4static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev){	unsigned char pin, irq;	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);	if (pin == 1) {		/* only allow INT A */		irq = pci_irq_swizzle[(PCI_HOST) hose->				      cfg_addr][PCI_DEV (dev)];		if (irq)			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);	}}#endifstruct pci_config_table gt_config_table[] = {	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},	{}};struct pci_controller pci0_hose = {#ifndef CONFIG_P3G4	fixup_irq:gt_fixup_irq,#endif	config_table:gt_config_table,};struct pci_controller pci1_hose = {#ifndef CONFIG_P3G4	fixup_irq:gt_fixup_irq,#endif	config_table:gt_config_table,};void pci_init_board (void){	unsigned int command;	pci0_hose.first_busno = 0;	pci0_hose.last_busno = 0xff;	local_buses[0] = pci0_hose.first_busno;	/* PCI memory space */	pci_set_region (pci0_hose.regions + 0,			CFG_PCI0_0_MEM_SPACE,			CFG_PCI0_0_MEM_SPACE,			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);	/* PCI I/O space */	pci_set_region (pci0_hose.regions + 1,			CFG_PCI0_IO_SPACE_PCI,			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);	pci_set_ops (&pci0_hose,		     pci_hose_read_config_byte_via_dword,		     pci_hose_read_config_word_via_dword,		     gt_read_config_dword,		     pci_hose_write_config_byte_via_dword,		     pci_hose_write_config_word_via_dword,		     gt_write_config_dword);	pci0_hose.region_count = 2;	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;	pci_register_hose (&pci0_hose);#ifndef CONFIG_P3G4	pciArbiterEnable (PCI_HOST0);	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);#endif	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);	command |= PCI_COMMAND_MASTER;	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);	command |= PCI_COMMAND_MEMORY;	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);	pci1_hose.first_busno = pci0_hose.last_busno + 1;	pci1_hose.last_busno = 0xff;	pci1_hose.current_busno = pci0_hose.current_busno;	local_buses[1] = pci1_hose.first_busno;	/* PCI memory space */	pci_set_region (pci1_hose.regions + 0,			CFG_PCI1_0_MEM_SPACE,			CFG_PCI1_0_MEM_SPACE,			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);	/* PCI I/O space */	pci_set_region (pci1_hose.regions + 1,			CFG_PCI1_IO_SPACE_PCI,			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);	pci_set_ops (&pci1_hose,		     pci_hose_read_config_byte_via_dword,		     pci_hose_read_config_word_via_dword,		     gt_read_config_dword,		     pci_hose_write_config_byte_via_dword,		     pci_hose_write_config_word_via_dword,		     gt_write_config_dword);	pci1_hose.region_count = 2;	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;	pci_register_hose (&pci1_hose);#ifndef CONFIG_P3G4	pciArbiterEnable (PCI_HOST1);	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);#endif	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);	command |= PCI_COMMAND_MASTER;	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);	command |= PCI_COMMAND_MEMORY;	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);}