/*********************************************************************** *M* Modul:         lwmon.cM*M* Content:       LWMON specific U-Boot commands. * * (C) Copyright 2001, 2002 * DENX Software Engineering * Wolfgang Denk, wd@denx.de * All rights reserved. *D* Design:        wd@denx.deC* Coding:        wd@denx.deV* Verification:  dzu@denx.de * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ***********************************************************************//*---------------------------- Headerfiles ----------------------------*/#include <common.h>#include <mpc8xx.h>#include <commproc.h>#include <i2c.h>#include <command.h>#include <malloc.h>#include <post.h>#include <serial.h>#include <linux/types.h>#include <linux/string.h>	/* for strdup *//*------------------------ Local prototypes ---------------------------*/static long int dram_size (long int, long int *, long int);static void kbd_init (void);static int compare_magic (uchar *kbd_data, uchar *str);/*--------------------- Local macros and constants --------------------*/#define	_NOT_USED_	0xFFFFFFFF#ifdef CONFIG_MODEM_SUPPORTstatic int key_pressed(void);extern void disable_putc(void);#endif /* CONFIG_MODEM_SUPPORT *//* * 66 MHz SDRAM access using UPM A */const uint sdram_table[] ={#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E)	/*	 * Single Read. (Offset 0 in UPM RAM)	 */	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,	0x1FF5FC47, /* last */	/*	 * SDRAM Initialization (offset 5 in UPM RAM)	 *	 * This is no UPM entry point. The following definition uses	 * the remaining space to establish an initialization	 * sequence, which is executed by a RUN command.	 *	 */		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */	/*	 * Burst Read. (Offset 8 in UPM RAM)	 */	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Single Write. (Offset 18 in UPM RAM)	 */	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Burst Write. (Offset 20 in UPM RAM)	 */	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */					    _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Refresh  (Offset 30 in UPM RAM)	 */	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,	0xFFFFFC84, 0xFFFFFC07, /* last */				_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Exception. (Offset 3c in UPM RAM)	 */	0x7FFFFC07, /* last */		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,#endif#ifdef CFG_MEMORY_7E	/*	 * Single Read. (Offset 0 in UPM RAM)	 */	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */	_NOT_USED_,	/*	 * SDRAM Initialization (offset 5 in UPM RAM)	 *	 * This is no UPM entry point. The following definition uses	 * the remaining space to establish an initialization	 * sequence, which is executed by a RUN command.	 *	 */		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */	/*	 * Burst Read. (Offset 8 in UPM RAM)	 */	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */					    _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Single Write. (Offset 18 in UPM RAM)	 */	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */					    _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Burst Write. (Offset 20 in UPM RAM)	 */	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,	0xE1BAFC04, 0x1FF5FC47, /* last */				_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Refresh  (Offset 30 in UPM RAM)	 */	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,	0xFFFFFC84, 0xFFFFFC07, /* last */				_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Exception. (Offset 3c in UPM RAM)	 */	0x7FFFFC07, /* last */		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,#endif};/* * Check Board Identity: * *//***********************************************************************F* Function:     int checkboard (void) P*A*Z* *P* Parameters:   noneP*P* Returnvalue:  int - 0 is always returned *Z* Intention:    This function is the checkboard() method implementationZ*               for the lwmon board.  Only a standard message is printed. *D* Design:       wd@denx.deC* Coding:       wd@denx.deV* Verification: dzu@denx.de ***********************************************************************/int checkboard (void){	puts ("Board: LICCON Konsole LCD3\n");	return (0);}/***********************************************************************F* Function:     long int initdram (int board_type) P*A*Z* *P* Parameters:   int board_typeP*                - Usually type of the board - ignored here.P*P* Returnvalue:  long intP*                - Size of initialized memory *Z* Intention:    This function is the initdram() method implementationZ*               for the lwmon board.Z*               The memory controller is initialized to access theZ*               DRAM. *D* Design:       wd@denx.deC* Coding:       wd@denx.deV* Verification: dzu@denx.de ***********************************************************************/long int initdram (int board_type){	volatile immap_t *immr = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immr->im_memctl;	long int size_b0;	long int size8, size9;	int i;	/*	 * Configure UPMA for SDRAM	 */	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));	memctl->memc_mptpr = CFG_MPTPR;	/* burst length=4, burst type=sequential, CAS latency=2 */	memctl->memc_mar = CFG_MAR;	/*	 * Map controller bank 3 to the SDRAM bank at preliminary address.	 */	memctl->memc_or3 = CFG_OR3_PRELIM;	memctl->memc_br3 = CFG_BR3_PRELIM;	/* initialize memory address register */	memctl->memc_mamr = CFG_MAMR_8COL;	/* refresh not enabled yet */	/* mode initialization (offset 5) */	udelay (200);				/* 0x80006105 */	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */	udelay (1);				/* 0x80006130 */	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);	udelay (1);				/* 0x80006130 */	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);	udelay (1);				/* 0x80006106 */	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */	udelay (200);	/* Need at least 10 DRAM accesses to stabilize */	for (i = 0; i < 10; ++i) {		volatile unsigned long *addr =			(volatile unsigned long *) SDRAM_BASE3_PRELIM;		unsigned long val;		val = *(addr + i);		*(addr + i) = val;	}	/*	 * Check Bank 0 Memory Size for re-configuration	 *	 * try 8 column mode	 */	size8 = dram_size (CFG_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);	udelay (1000);	/*	 * try 9 column mode	 */	size9 = dram_size (CFG_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);	if (size8 < size9) {		/* leave configuration at 9 columns */		size_b0 = size9;		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE;		udelay (500);	} else {			/* back to 8 columns            */		size_b0 = size8;		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;		udelay (500);	}	/*	 * Final mapping:	 */	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;	udelay (1000);	return (size_b0);}/***********************************************************************F* Function:     static long int dram_size (long int mamr_value,F*                                          long int *base,F*                                          long int maxsize) P*A*Z* *P* Parameters:   long int mamr_valueP*                - Value for MAMR for the testP*               long int *baseP*                - Base address for the testP*               long int maxsizeP*                - Maximum size to test forP*P* Returnvalue:  long intP*                - Size of probed memory *Z* Intention:    Check memory range for valid RAM. A simple memory testZ*               determines the actually available RAM size betweenZ*               addresses `base' and `base + maxsize'. Some (not all)Z*               hardware errors are detected:Z*                - short between address linesZ*                - short between data lines *D* Design:       wd@denx.deC* Coding:       wd@denx.deV* Verification: dzu@denx.de ***********************************************************************/static long int dram_size (long int mamr_value, long int *base, long int maxsize){	volatile immap_t *immr = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immr->im_memctl;	memctl->memc_mamr = mamr_value;	return (get_ram_size(base, maxsize));}/* ------------------------------------------------------------------------- */#ifndef	PB_ENET_TENA# define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */#endif/***********************************************************************F* Function:     int board_early_init_f (void) P*A*Z* *P* Parameters:   noneP*P* Returnvalue:  intP*                - 0 is always returned. *Z* Intention:    This function is the board_early_init_f() method implementationZ*               for the lwmon board.Z*               Disable Ethernet TENA on Port B. *D* Design:       wd@denx.deC* Coding:       wd@denx.deV* Verification: dzu@denx.de ***********************************************************************/