\   00000028   1B49               LDR         R1,??AT91F_LowLevelInit_0+0x8  ;; 0xfffffc68
   \   0000002A   0968               LDR         R1,[R1, #+0]
   \   0000002C   0907               LSL         R1,R1,#+0x1C
   \   0000002E   FBD5               BPL         ??AT91F_LowLevelInit_3
     62          
     63              /////////////////////////////////////////////////////////////////////////////////////////////////////
     64              // Init PMC Step 3.
     65              // Selection of Master Clock MCK (equal to Processor Clock PCK) equal to PLL/2 = 48MHz
     66              // The PMC_MCKR register must not be programmed in a single write operation (see. Product Errata Sheet)
     67              /////////////////////////////////////////////////////////////////////////////////////////////////////
     68              AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
   \   00000030   1C49               LDR         R1,??AT91F_LowLevelInit_0+0x14  ;; 0xfffffc30
   \   00000032   0422               MOV         R2,#+0x4
   \   00000034   0A60               STR         R2,[R1, #+0]
     69              // Wait until the master clock is established
     70              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_4:
   \   00000036   1849               LDR         R1,??AT91F_LowLevelInit_0+0x8  ;; 0xfffffc68
   \   00000038   0968               LDR         R1,[R1, #+0]
   \   0000003A   0907               LSL         R1,R1,#+0x1C
   \   0000003C   FBD5               BPL         ??AT91F_LowLevelInit_4
     71          
     72              AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
   \   0000003E   1949               LDR         R1,??AT91F_LowLevelInit_0+0x14  ;; 0xfffffc30
   \   00000040   184A               LDR         R2,??AT91F_LowLevelInit_0+0x14  ;; 0xfffffc30
   \   00000042   1268               LDR         R2,[R2, #+0]
   \   00000044   0323               MOV         R3,#+0x3
   \   00000046   1343               ORR         R3,R2
   \   00000048   0B60               STR         R3,[R1, #+0]
     73              // Wait until the master clock is established
     74              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_5:
   \   0000004A   1349               LDR         R1,??AT91F_LowLevelInit_0+0x8  ;; 0xfffffc68
   \   0000004C   0968               LDR         R1,[R1, #+0]
   \   0000004E   0907               LSL         R1,R1,#+0x1C
   \   00000050   FBD5               BPL         ??AT91F_LowLevelInit_5
     75          
     76              /////////////////////////////////////////////////////////////////////////////////////////////////////
     77              //  Disable Watchdog (write once register)
     78              /////////////////////////////////////////////////////////////////////////////////////////////////////
     79              AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
   \   00000052   1549               LDR         R1,??AT91F_LowLevelInit_0+0x18  ;; 0xfffffd44
   \   00000054   8022               MOV         R2,#+0x80
   \   00000056   1202               LSL         R2,R2,#+0x8        ;; #+0x8000
   \   00000058   0A60               STR         R2,[R1, #+0]
     80          
     81              /////////////////////////////////////////////////////////////////////////////////////////////////////
     82              //  Enable User Reset: assertion of the Reset Length programmed to 1ms
     83              /////////////////////////////////////////////////////////////////////////////////////////////////////
     84              AT91C_BASE_RSTC->RSTC_RMR = AT91C_RSTC_URSTEN | (0x4<<8) | ((unsigned int) 0xA5 <<24);
   \   0000005A   1449               LDR         R1,??AT91F_LowLevelInit_0+0x1C  ;; 0xfffffd08
   \   0000005C   144A               LDR         R2,??AT91F_LowLevelInit_0+0x20  ;; 0xa5000401
   \   0000005E   0A60               STR         R2,[R1, #+0]
     85          
     86              ////////////////////////////////////////////////////////////////////////////////////////////////////
     87              //  Init AIC: assign corresponding handler for each interrupt source
     88              /////////////////////////////////////////////////////////////////////////////////////////////////////
     89              AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
   \   00000060   1449               LDR         R1,??AT91F_LowLevelInit_0+0x24  ;; 0xfffff080
   \   00000062   154A               LDR         R2,??AT91F_LowLevelInit_0+0x28  ;; AT91F_Default_FIQ_handler
   \   00000064   0A60               STR         R2,[R1, #+0]
     90              for (i = 1; i < 31; i++) {
   \   00000066   0121               MOV         R1,#+0x1
   \   00000068   081C               MOV         R0,R1
   \                     ??AT91F_LowLevelInit_6:
   \   0000006A   0006               LSL         R0,R0,#+0x18       ;; ZeroExt     R0,R0,#+0x18,#+0x18
   \   0000006C   000E               LSR         R0,R0,#+0x18
   \   0000006E   1F28               CMP         R0,#+0x1F
   \   00000070   08D2               BCS         ??AT91F_LowLevelInit_7
     91                  AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
   \   00000072   0006               LSL         R0,R0,#+0x18       ;; ZeroExt     R0,R0,#+0x18,#+0x18
   \   00000074   000E               LSR         R0,R0,#+0x18
   \   00000076   0421               MOV         R1,#+0x4
   \   00000078   4143               MUL         R1,R0
   \   0000007A   0E4A               LDR         R2,??AT91F_LowLevelInit_0+0x24  ;; 0xfffff080
   \   0000007C   0F4B               LDR         R3,??AT91F_LowLevelInit_0+0x2C  ;; AT91F_Default_IRQ_handler
   \   0000007E   5350               STR         R3,[R2, R1]
     92              }
   \   00000080   401C               ADD         R0,#+0x1
   \   00000082   F2E7               B           ??AT91F_LowLevelInit_6
     93              AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
   \                     ??AT91F_LowLevelInit_7:
   \   00000084   0E49               LDR         R1,??AT91F_LowLevelInit_0+0x30  ;; 0xfffff134
   \   00000086   0F4A               LDR         R2,??AT91F_LowLevelInit_0+0x34  ;; AT91F_Spurious_handler
   \   00000088   0A60               STR         R2,[R1, #+0]
     94          }
   \   0000008A   01BC               POP         {R0}
   \   0000008C   0047               BX          R0                 ;; return
   \   0000008E   C046               NOP         
   \                     ??AT91F_LowLevelInit_0:
   \   00000090   20FCFFFF           DC32        0xfffffc20
   \   00000094   01400000           DC32        0x4001
   \   00000098   68FCFFFF           DC32        0xfffffc68
   \   0000009C   2CFCFFFF           DC32        0xfffffc2c
   \   000000A0   0E3F4810           DC32        0x10483f0e
   \   000000A4   30FCFFFF           DC32        0xfffffc30
   \   000000A8   44FDFFFF           DC32        0xfffffd44
   \   000000AC   08FDFFFF           DC32        0xfffffd08
   \   000000B0   010400A5           DC32        0xa5000401
   \   000000B4   80F0FFFF           DC32        0xfffff080
   \   000000B8   ........           DC32        AT91F_Default_FIQ_handler
   \   000000BC   ........           DC32        AT91F_Default_IRQ_handler
   \   000000C0   34F1FFFF           DC32        0xfffff134
   \   000000C4   ........           DC32        AT91F_Spurious_handler

   Maximum stack usage in bytes:

     Function           CSTACK
     --------           ------
     AT91F_LowLevelInit     4


   Segment part sizes:

     Function/Label     Bytes
     --------------     -----
     AT91F_LowLevelInit  200
      Others               8

 
 208 bytes in segment CODE
 
 200 bytes of CODE memory (+ 8 bytes shared)

Errors: none
Warnings: none