/**********************************************************************
*
*         (C) COPYRIGHT 2004 FREESCALE, INC.
*         ALL RIGHTS RESERVED
*
*
*     Group/Division:  WMSG/MMDO
*
*     Description:
*
*     Related Specifications:
*
*     Errata:
*
*     File Name:        MX21_UART2.h
*     Revision Number:  0.1
*     Author(s):        Ryan Johnson
*     Date created:     12 June 2004
*     Revision History:
*        Date      Rev     Description
*        ----      ---     -----------
*        12June04  0.1     First draft
*
**********************************************************************/

#ifndef _MX21UART2_H_
#define _MX21UART2_H_

#include "MX21_MemMap.h"
#include "MX21_Macros.h"
#include "MX21_DataTypes.h"
#include "MX21_Common.h"

/********************************************************************
M A C R O S
*********************************************************************/

#define _8bitUART                 1
#define _7bitUART                 0
#define _OddParity                0
#define _EvenParity               1
#define _16xBaud                  0
#define _UARTRefClock             1


#define BAUD_300     300	    // 300 baud 
#define BAUD_600     600	    // 600 baud 
#define BAUD_1200    1200	    // 1200 baud 
#define BAUD_2400    2400	    // 2400 baud 
#define BAUD_4800    4800	    // 4800 baud 
#define BAUD_9600    9600	    // 9600 baud      
#define BAUD_14400   14400	    // 14400 baud 
#define BAUD_19200   19200	    // 19200 baud 
#define BAUD_28800   28800	    // 28800 baud 
#define BAUD_38400   38400	    // 38400 baud 
#define BAUD_57600   57600	    // 57600 baud 
#define BAUD_115200  115200	    // 115200 baud 
#define BAUD_230400  230400	    // 230400 baud 
#define BAUD_460800  460800	    // 460800 baud 
#define BAUD_812500  812500	    // 812500 baud 
#define BAUD_920000  920000	    // 920000 baud
#define BAUD_1152000 1152000    // 1152000 baud 
/********************************************************************
F U N C T I O N   P R O T O T Y P E S
*********************************************************************/


// Make a demo with loopback

void
uart2_Demo(void);

/*---------------------------------------------------
// InterruptHandler
// Needs to be linked to in the vect_IRQ table in
//  IntHandlers.h
// Provides hooks for the various UART interrupt
//  possiblities.
//-------------------------------------------------*/
void
uart2_DemoInterruptHandler(void);

/*---------------------------------------------------
// AutoBRMFast
// Configures RFDIV and the BRM numerator and divider
// according to the parameter which should be the
// desired baud rate. Returns 0 if failed,
// otherwise returns the actual programmed baud rate.
// This version does not 'thoroughly' investigate
//  the full spectrum of closely matched fractions,
//  but simply uses a fraction with a denominator of
//  65535. As a result there may be up to .0008%
//  divergence from the closest possible match.
//-------------------------------------------------*/
uint32_t
uart2_AutoBRMFast(uint32_t);//

/*---------------------------------------------------
// AutoBRMPrecise
// Configures RFDIV and the BRM numerator and divider
// according to the parameter which should be the
// desired baud rate. Returns 0 if failed,
// otherwise returns the actual programmed baud rate.
// This version will try the full spectrum of
//  denominators in order to find the closest
//  programable match. This results in a for loop
//  with several instructions being run ~100,000
//  times.
//-------------------------------------------------*/
uint32_t
uart2_AutoBRMPrecise(uint32_t);//





/*---------------------------------------------------
// CHARRDY, URXD[15]
//  Character Ready --Indicates an invalid read
//  when the RxFIFO is empty and the software
//  attempts to read the previously read data.
// Returns:
//	0 = The character in the RX_DATA field and
//	 its associated flags are invalid.
//	1 = The character in the RX_DATA field and
//	 its associated flags are valid and ready
//	 to read
//-------------------------------------------------*/
 uint32_t
uart2_RxCharacterReady(void);//


/*---------------------------------------------------
// ERR, URXD[14]
//  Error Detect --Indicates whether the character
//  present in the RX_DATA field has an error
//  (OVRRUN, FRMERR, BRK or PRERR) status. The ERR
//  bit is updated and valid for each received
//  character.
// Returns:
//	0 = An error status was detected
//	1 = No error status was detected
//-------------------------------------------------*/
 uint32_t
uart2_RxCharacterClean(void);//


/*---------------------------------------------------
// OVRRUN, URXD[13]
//  Receiver Overrun --Indicates whether the
//  receiver ignored data to prevent overwriting
//  the data in the RxFIFO. This error indicates
//  that the software is not keeping up with the
//  incoming data rate. OVRRUN is set for the last
//  (32nd) character written to the RxFIFO to
//  indicate that all characters following this
//  character will be ignored if a read is not
//  performed by the software. OVRRUN is updated
//  and valid for each received character. Under
//  normal circumstances, OVRRUN is never set.
// Returns:
//	0 = No RxFIFO overrun was detected
//	1 = A RxFIFO overrun was detected
//-------------------------------------------------*/
 uint32_t
uart2_RxFIFO_OverrunError(void);//


/*---------------------------------------------------
// FRMERR, URXD[12]
//  Frame Error --Indicates whether the current
//  character had a framing error (a missing stop
//  bit) and is possibly corrupted. FRMERR is
//  updated for each character read from the
//  RxFIFO.
// Returns:
//	0 = The current character has no framing
//	 error
//	1 = The current character has a framing
//	 error
//-------------------------------------------------*/
 uint32_t
uart2_RxFrameError(void);//


/*---------------------------------------------------
// BRK, URXD[11]
//  BREAK Detect --Indicates whether the current
//  character was detected as a BREAK character.
//  The data bits and the stop bit are all 0. The
//  FRMERR bit is set when BRK is set. When odd
//  parity is selected, PRERR is also set when BRK
//  is set. BRK is valid for each character read
//  from the RxFIFO.
// Returns:
//	0 = The current character is not a BREAK
//	 character
//	1 = The current character is a BREAK
//	 character
//-------------------------------------------------*/
 uint32_t
uart2_RxBreakDetect(void);//


/*---------------------------------------------------
// PRERR, URXD[10]
//  Parity Error --Indicates whether the current
//  character was detected with a parity error and
//  is possibly corrupted. PRERR is updated for
//  each character read from the RxFIFO. When
//  parity is disabled, PRERR always reads as 0.
// Returns:
//	0 = No parity error was detected for data
//	 in the RX_DATA field
//	1 = A parity error was detected for data in
//	 the RX_DATA field
//-------------------------------------------------*/
 uint32_t
uart2_RxParityError(void);//


/*---------------------------------------------------
// RX_DATA, URXD[7-0]
//  Received Data --Holds the received character.
//  In 7-bit mode, the most significant bit (MSB)
//  is forced to 0. In 8-bit mode, all bits are
//  active. Support 8-bit data read for DMA
//  transfer. When DMA is configured to 8-bit port
//  reading from RxFIFO, the status bits are
//  ignored and only RX_DATA are transferred.
//-------------------------------------------------*/
 uint32_t
uart2_RxCharacter(void);//

/*---------------------------------------------------
// TX_DATA, UTXD[7-0]
//  Transmit Data --Holds the parallel transmit
//  data inputs. In 7-bit mode, D7 is ignored. In
//  8-bit mode, all bits are used. Data is
//  transmitted least significant bit (LSB) first.
//  A new character is transmitted when the TX_DATA
//  field is written. The TX_DATA field must be
//  written only when the TRDY bit is high to
//  ensure that corrupted data is not sent.
//-------------------------------------------------*/
 void
uart2_TxCharacter(uint32_t);//


/*---------------------------------------------------
// ADEN, UCR1[15] = Enable/Disable
//
//  Automatic Baud Rate Detection Interrupt
//  Enable --Enables or disables the automatic baud
//  rate detect complete (ADET) bit to generate an
//  interrupt.
//-------------------------------------------------*/
 void
uart2_AutoBaudInterrupt(uint32_t);//


/*---------------------------------------------------
// ADBR, UCR1[14] = Enable/Disable
//
//  Automatic Detection of Baud Rate
//  --Enables/Disables automatic baud rate
//  detection. When the ADBR bit is set and the
//  ADET bit is cleared, the receiver detects the
//  incoming baud rate automatically. The ADET flag
//  is set when the receiver verifies that the
//  incoming baud rate is detected properly by
//  detecting an ASCII character "A" or
//  "a" (0x61 or 0x41).
//-------------------------------------------------*/
 void
uart2_AutoBaud(uint32_t);//


/*---------------------------------------------------
// TRDYEN, UCR1[13] = Enable/Disable
//
//  Transmitter Ready Interrupt Enable
//  --Enables/Disables the transmitter Ready
//  Interrupt (TRDY) when the transmitter has one
//  or more slots available in the TxFIFO. The fill
//  level in the TXFIFO at which an interrupt is
//  generated is controlled by TxTL bits. When
//  TRDYEN is negated, the transmitter ready
//  interrupt is disabled.
//-------------------------------------------------*/
 void
uart2_TxFIFO_ReadyInterrupt(uint32_t);//


/*---------------------------------------------------
// IDEN, UCR1[12] = Enable/Disable
//
//  Idle Condition Detected Interrupt Enable
//  --Enables/Disables the IDLE bit to generate an
//  interrupt.
//-------------------------------------------------*/
 void
uart2_RxIdleDetectInterrupt(uint32_t);//


/*---------------------------------------------------
// ICD, UCR1[11-10] = 0..3
//   Result: Idle is (n+2)^2 frames.
//
//  Idle Condition Detect --Controls the number
//  of frames RXD is allowed to be idle before an
//  idle condition is reported.
//-------------------------------------------------*/
 void
uart2_RxIdleLength(uint32_t);//


/*---------------------------------------------------
// RRDYEN, UCR1[9] = Enable/Disable
//
//  Receiver Ready Interrupt Enable
//  --Enables/Disables the RRDY interrupt when the
//  RxFIFO contains data. The fill level in the
//  RXFIFO at which an interrupt is generated is
//  controlled by the RXTL bits. When RRDYEN is
//  negated, the receiver ready interrupt is
//  disabled.
//-------------------------------------------------*/
 void
uart2_RxFIFO_TriggerReadyInterrupt(uint32_t);//


/*---------------------------------------------------
// RXDMAEN, UCR1[8] = Enable/Disable
//
//  Receive Ready DMA Enable --Enables/Disables
//  the receive DMA request IPD_UART_RX_DMAREQ when
//  the receiver has data in the RxFIFO. The fill
//  level in the RxFIFO at which a DMA request is
//  generated is controlled by the RXFL bits. When
//  negated, the receive DMA request is disabled.
//-------------------------------------------------*/
 void
uart2_RxFIFO_TriggerReadyDMA(uint32_t);//


/*---------------------------------------------------
// IREN, UCR1[7] = Enable/Disable
//
//  Infrared Interface Enable
//  --Enables/Disables the IR interface. See the IR
//  interface description in for more information.
//-------------------------------------------------*/
 void
uart2_IR(uint32_t);


/*---------------------------------------------------
// TXMPTYEN, UCR1[6] = Enable/Disable
//
//  Transmitter Empty Interrupt Enable
//  --Enables/Disables the transmitter FIFO empty
//  (TXFE) interrupt. When negated, the TXFE
//  interrupt is disabled.