?? mcbsp55x.h
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/******************************************************************************/
/* MCBSP55X.H - MCBSP55X routines header file. */
/* */
/* This module provides the devlib implementation for the MCBSP */
/* on the TMS320C55x DSP. */
/* */
/* MACRO FUNCTIONS: */
/* */
/* FUNCTIONS: */
/* mcbsp_init - initialize and start serial port operation */
/* */
/* */
/******************************************************************************/
/******************************************************************/
/* This header file defines the data structures and macros to */
/* necessary to address the Multi-Channel Serial Port */
/******************************************************************/
#ifndef _MCBSP55X_H_
#define _MCBSP55X_H_
#include "regs55x.h"
/*********************************************************************/
/* Register Definition MCBSP */
/*********************************************************************/
#define DRR2_ADDR(port) (0x2800+(0x400*port))
#define DRR2(port) *(ioport volatile unsigned int *)DRR2_ADDR(port)
#define DRR1_ADDR(port) (DRR2_ADDR(port)+1)
#define DRR1(port) *(ioport volatile unsigned int *)DRR1_ADDR(port)
#define DXR2_ADDR(port) (DRR2_ADDR(port)+2)
#define DXR2(port) *(ioport volatile unsigned int *)DXR2_ADDR(port)
#define DXR1_ADDR(port) (DRR2_ADDR(port)+3)
#define DXR1(port) *(ioport volatile unsigned int *)DXR1_ADDR(port)
#define SPCR2_ADDR(port) (DRR2_ADDR(port)+4)
#define SPCR2(port) *(ioport volatile unsigned int *)SPCR2_ADDR(port)
#define SPCR1_ADDR(port) (DRR2_ADDR(port)+5)
#define SPCR1(port) *(ioport volatile unsigned int *)SPCR1_ADDR(port)
#define RCR2_ADDR(port) (DRR2_ADDR(port)+6)
#define RCR2(port) *(ioport volatile unsigned int *)RCR2_ADDR(port)
#define RCR1_ADDR(port) (DRR2_ADDR(port)+7)
#define RCR1(port) *(ioport volatile unsigned int *)RCR1_ADDR(port)
#define XCR2_ADDR(port) (DRR2_ADDR(port)+8)
#define XCR2(port) *(ioport volatile unsigned int *)XCR2_ADDR(port)
#define XCR1_ADDR(port) (DRR2_ADDR(port)+9)
#define XCR1(port) *(ioport volatile unsigned int *)XCR1_ADDR(port)
#define SRGR2_ADDR(port) (DRR2_ADDR(port)+10)
#define SRGR2(port) *(ioport volatile unsigned int *)SRGR2_ADDR(port)
#define SRGR1_ADDR(port) (DRR2_ADDR(port)+11)
#define SRGR1(port) *(ioport volatile unsigned int *)SRGR1_ADDR(port)
#define MCR2_ADDR(port) (DRR2_ADDR(port)+12)
#define MCR2(port) *(ioport volatile unsigned int *)MCR2_ADDR(port)
#define MCR1_ADDR(port) (DRR2_ADDR(port)+13)
#define MCR1(port) *(ioport volatile unsigned int *)MCR1_ADDR(port)
#define RCERA_ADDR(port) (DRR2_ADDR(port)+14)
#define RCERA(port) *(ioport volatile unsigned int *)RCERA_ADDR(port)
#define RCERB_ADDR(port) (DRR2_ADDR(port)+15)
#define RCERB(port) *(ioport volatile unsigned int *)RCERB_ADDR(port)
#define XCERA_ADDR(port) (DRR2_ADDR(port)+16)
#define XCERA(port) *(ioport volatile unsigned int *)XCERA_ADDR(port)
#define XCERB_ADDR(port) (DRR2_ADDR(port)+17)
#define XCERB(port) *(ioport volatile unsigned int *)XCERB_ADDR(port)
#define PCR_ADDR(port) (DRR2_ADDR(port)+18)
#define PCR(port) *(ioport volatile unsigned int *)PCR_ADDR(port)
#define RCERC_ADDR(port) (DRR2_ADDR(port)+19)
#define RCERC(port) *(ioport volatile unsigned int *)RCERC_ADDR(port)
#define RCERD_ADDR(port) (DRR2_ADDR(port)+20)
#define RCERD(port) *(ioport volatile unsigned int *)RCERD_ADDR(port)
#define XCERC_ADDR(port) (DRR2_ADDR(port)+21)
#define XCERC(port) *(ioport volatile unsigned int *)XCERC_ADDR(port)
#define XCERD_ADDR(port) (DRR2_ADDR(port)+22)
#define XCERD(port) *(ioport volatile unsigned int *)XCERD_ADDR(port)
#define RCERE_ADDR(port) (DRR2_ADDR(port)+23)
#define RCERE(port) *(ioport volatile unsigned int *)RCERE_ADDR(port)
#define RCERF_ADDR(port) (DRR2_ADDR(port)+24)
#define RCERF(port) *(ioport volatile unsigned int *)RCERF_ADDR(port)
#define XCERE_ADDR(port) (DRR2_ADDR(port)+25)
#define XCERE(port) *(ioport volatile unsigned int *)XCERE_ADDR(port)
#define XCERF_ADDR(port) (DRR2_ADDR(port)+26)
#define XCERF(port) *(ioport volatile unsigned int *)XCERF_ADDR(port)
#define RCERG_ADDR(port) (DRR2_ADDR(port)+27)
#define RCERG(port) *(ioport volatile unsigned int *)RCERG_ADDR(port)
#define RCERH_ADDR(port) (DRR2_ADDR(port)+28)
#define RCERH(port) *(ioport volatile unsigned int *)RCERH_ADDR(port)
#define XCERG_ADDR(port) (DRR2_ADDR(port)+29)
#define XCERG(port) *(ioport volatile unsigned int *)XCERG_ADDR(port)
#define XCERH_ADDR(port) (DRR2_ADDR(port)+30)
#define XCERH(port) *(ioport volatile unsigned int *)XCERH_ADDR(port)
/*********************************************************************/
/* MCBSP 0 */
/*********************************************************************/
/*
#define DRR20_ADDR 0x2800
#define DRR20 *(ioport volatile unsigned int *)DRR20_ADDR
#define DRR10_ADDR (DRR20_ADDR+1)
#define DRR10 *(ioport volatile unsigned int *)DRR10_ADDR
#define DXR20_ADDR (DRR20_ADDR+2)
#define DXR20 *(ioport volatile unsigned int *)DXR20_ADDR
#define DXR10_ADDR (DRR20_ADDR+3)
#define DXR10 *(ioport volatile unsigned int *)DXR10_ADDR
#define SPCR20_ADDR (DRR20_ADDR+4)
#define SPCR20 *(ioport volatile unsigned int *)SPCR20_ADDR
#define SPCR10_ADDR (DRR20_ADDR+5)
#define SPCR10 *(ioport volatile unsigned int *)SPCR10_ADDR
#define RCR20_ADDR (DRR20_ADDR+6)
#define RCR20 *(ioport volatile unsigned int *)RCR10_ADDR
#define RCR10_ADDR (DRR20_ADDR+7)
#define RCR10 *(ioport volatile unsigned int *)RCR20_ADDR
#define XCR20_ADDR (DRR20_ADDR+8)
#define XCR20 *(ioport volatile unsigned int *)XCR20_ADDR
#define XCR10_ADDR (DRR20_ADDR+9)
#define XCR10 *(ioport volatile unsigned int *)XCR10_ADDR
#define SRGR20_ADDR (DRR20_ADDR+10)
#define SRGR20 *(ioport volatile unsigned int *)SRGR20_ADDR
#define SRGR10_ADDR (DRR20_ADDR+11)
#define SRGR10 *(ioport volatile unsigned int *)SRGR10_ADDR
#define MCR20_ADDR (DRR20_ADDR+12)
#define MCR20 *(ioport volatile unsigned int *)MCR20_ADDR
#define MCR10_ADDR (DRR20_ADDR+13)
#define MCR10 *(ioport volatile unsigned int *)MCR10_ADDR
#define RCERA0_ADDR (DRR20_ADDR+14)
#define RCERA0 *(ioport volatile unsigned int *)RCERA0_ADDR
#define RCERB0_ADDR (DRR20_ADDR+15)
#define RCERB0 *(ioport volatile unsigned int *)RCERB0_ADDR
#define XCERA0_ADDR (DRR20_ADDR+16)
#define XCERA0 *(ioport volatile unsigned int *)XCERA0_ADDR
#define XCERB0_ADDR (DRR20_ADDR+17)
#define XCERB0 *(ioport volatile unsigned int *)XCERB0_ADDR
#define PCR0_ADDR (DRR20_ADDR+18)
#define PCR0 *(ioport volatile unsigned int *)PCR0_ADDR
#define RCERC0_ADDR (DRR20_ADDR+19)
#define RCERC0 *(ioport volatile unsigned int *)RCERC0_ADDR
#define RCERD0_ADDR (DRR20_ADDR+20)
#define RCERD0 *(ioport volatile unsigned int *)RCERD0_ADDR
#define XCERC0_ADDR (DRR20_ADDR+21)
#define XCERC0 *(ioport volatile unsigned int *)XCERC0_ADDR
#define XCERD0_ADDR (DRR20_ADDR+22)
#define XCERD0 *(ioport volatile unsigned int *)XCERD0_ADDR
#define RCERE0_ADDR (DRR20_ADDR+23)
#define RCERE0 *(ioport volatile unsigned int *)RCERE0_ADDR
#define RCERF0_ADDR (DRR20_ADDR+24)
#define RCERF0 *(ioport volatile unsigned int *)RCERF0_ADDR
#define XCERE0_ADDR (DRR20_ADDR+25)
#define XCERE0 *(ioport volatile unsigned int *)XCERE0_ADDR
#define XCERF0_ADDR (DRR20_ADDR+26)
#define XCERF0 *(ioport volatile unsigned int *)XCERF0_ADDR
#define RCERG0_ADDR (DRR20_ADDR+27)
#define RCERG0 *(ioport volatile unsigned int *)RCERG0_ADDR
#define RCERH0_ADDR (DRR20_ADDR+28)
#define RCERH0 *(ioport volatile unsigned int *)RCERH0_ADDR
#define XCERG0_ADDR (DRR20_ADDR+29)
#define XCERG0 *(ioport volatile unsigned int *)XCERG0_ADDR
#define XCERH0_ADDR (DRR20_ADDR+30)
#define XCERH0 *(ioport volatile unsigned int *)XCERH0_ADDR
*/
/*********************************************************************/
/* MCBSP 1 */
/*********************************************************************/
/*
#define DRR21_ADDR 0x2800
#define DRR21 *(ioport volatile unsigned int *)DRR21_ADDR
#define DRR11_ADDR (DRR21_ADDR+1)
#define DRR11 *(ioport volatile unsigned int *)DRR11_ADDR
#define DXR21_ADDR (DRR21_ADDR+2)
#define DXR21 *(ioport volatile unsigned int *)DXR21_ADDR
#define DXR11_ADDR (DRR21_ADDR+3)
#define DXR11 *(ioport volatile unsigned int *)DXR11_ADDR
#define SPCR21_ADDR (DRR21_ADDR+4)
#define SPCR21 *(ioport volatile unsigned int *)SPCR21_ADDR
#define SPCR11_ADDR (DRR21_ADDR+5)
#define SPCR11 *(ioport volatile unsigned int *)SPCR11_ADDR
#define RCR21_ADDR (DRR21_ADDR+6)
#define RCR21 *(ioport volatile unsigned int *)RCR11_ADDR
#define RCR11_ADDR (DRR21_ADDR+7)
#define RCR11 *(ioport volatile unsigned int *)RCR21_ADDR
#define XCR21_ADDR (DRR21_ADDR+8)
#define XCR21 *(ioport volatile unsigned int *)XCR21_ADDR
#define XCR11_ADDR (DRR21_ADDR+9)
#define XCR11 *(ioport volatile unsigned int *)XCR11_ADDR
#define SRGR21_ADDR (DRR21_ADDR+10)
#define SRGR21 *(ioport volatile unsigned int *)SRGR21_ADDR
#define SRGR11_ADDR (DRR21_ADDR+11)
#define SRGR11 *(ioport volatile unsigned int *)SRGR11_ADDR
#define MCR21_ADDR (DRR21_ADDR+12)
#define MCR21 *(ioport volatile unsigned int *)MCR21_ADDR
#define MCR11_ADDR (DRR21_ADDR+13)
#define MCR11 *(ioport volatile unsigned int *)MCR11_ADDR
#define RCERA1_ADDR (DRR21_ADDR+14)
#define RCERA1 *(ioport volatile unsigned int *)RCERA1_ADDR
#define RCERB1_ADDR (DRR21_ADDR+15)
#define RCERB1 *(ioport volatile unsigned int *)RCERB1_ADDR
#define XCERA1_ADDR (DRR21_ADDR+16)
#define XCERA1 *(ioport volatile unsigned int *)XCERA1_ADDR
#define XCERB1_ADDR (DRR21_ADDR+17)
#define XCERB1 *(ioport volatile unsigned int *)XCERB1_ADDR
#define PCR1_ADDR (DRR21_ADDR+18)
#define PCR1 *(ioport volatile unsigned int *)PCR1_ADDR
#define RCERC1_ADDR (DRR21_ADDR+19)
#define RCERC1 *(ioport volatile unsigned int *)RCERC1_ADDR
#define RCERD1_ADDR (DRR21_ADDR+20)
#define RCERD1 *(ioport volatile unsigned int *)RCERD1_ADDR
#define XCERC1_ADDR (DRR21_ADDR+21)
#define XCERC1 *(ioport volatile unsigned int *)XCERC1_ADDR
#define XCERD1_ADDR (DRR21_ADDR+22)
#define XCERD1 *(ioport volatile unsigned int *)XCERD1_ADDR
#define RCERE1_ADDR (DRR21_ADDR+23)
#define RCERE1 *(ioport volatile unsigned int *)RCERE1_ADDR
#define RCERF1_ADDR (DRR21_ADDR+24)
#define RCERF1 *(ioport volatile unsigned int *)RCERF1_ADDR
#define XCERE1_ADDR (DRR21_ADDR+25)
#define XCERE1 *(ioport volatile unsigned int *)XCERE1_ADDR
#define XCERF1_ADDR (DRR21_ADDR+26)
#define XCERF1 *(ioport volatile unsigned int *)XCERF1_ADDR
#define RCERG1_ADDR (DRR21_ADDR+27)
#define RCERG1 *(ioport volatile unsigned int *)RCERG1_ADDR
#define RCERH1_ADDR (DRR21_ADDR+28)
#define RCERH1 *(ioport volatile unsigned int *)RCERH1_ADDR
#define XCERG1_ADDR (DRR21_ADDR+29)
#define XCERG1 *(ioport volatile unsigned int *)XCERG1_ADDR
#define XCERH1_ADDR (DRR21_ADDR+30)
#define XCERH1 *(ioport volatile unsigned int *)XCERH1_ADDR
*/
/*********************************************************************/
/* MCBSP 2 */
/*********************************************************************/
/*
#define DRR22_ADDR 0x2800
#define DRR22 *(ioport volatile unsigned int *)DRR22_ADDR
#define DRR12_ADDR (DRR22_ADDR+1)
#define DRR12 *(ioport volatile unsigned int *)DRR12_ADDR
#define DXR22_ADDR (DRR22_ADDR+2)
#define DXR22 *(ioport volatile unsigned int *)DXR22_ADDR
#define DXR12_ADDR (DRR22_ADDR+3)
#define DXR12 *(ioport volatile unsigned int *)DXR12_ADDR
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