REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET,		   IXP425_PCI_AHBIOBASE_DEFAULT);	REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET,		   IXP425_PCI_PCIMEMBASE_DEFAULT);	crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);	REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);	regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS;	REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);	crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);	udelay (1000);	pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD);	REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE		   | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);#ifdef CONFIG_PCI_SCAN_SHOW	printf ("Device  bus  dev  func  deviceID  vendorID \n");#endif	pci_bus_scan ();}void configure_pins (void){	unsigned int regval;	/* Disable clock on GPIO PIN 14 */	READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);	WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8)));	READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);	READ_GPIO_REG (IXP425_GPIO_GPOER, regval);	WRITE_GPIO_REG (IXP425_GPIO_GPOER,			(((~(3 << 13)) & regval) | (0xf << 8)));	READ_GPIO_REG (IXP425_GPIO_GPOER, regval);	READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);	WRITE_GPIO_REG (IXP425_GPIO_GPIT2R,			(regval &			 ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1)));	READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);	READ_GPIO_REG (IXP425_GPIO_GPISR, regval);	WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8)));	READ_GPIO_REG (IXP425_GPIO_GPISR, regval);}void sys_pci_gpio_clock_config (void){	unsigned int regval;	READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);	regval |= 0x1 << 4;	WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);	READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);	regval |= 0x1 << 8;	WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);}void pci_bus_scan (void){	unsigned int bus = 0, dev, func = 0;	unsigned short data16;	unsigned int data32;	unsigned char intPin;	/* Assign first device to ourselves */	devices[0].bus = 0;	devices[0].device = 0;	devices[0].func = 0;	crp_read (PCI_CFG_VENDOR_ID, &data32);	devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK;	devices[0].device_id = data32 >> 16;	devices[0].error = FALSE;	devices[0].bar[NO_BAR].size = 0;	/*dummy - required */	nDevices = 1;	nMBars = 0;	nIOBars = 0;	for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) {		/*Check whether a device is present */		if (pci_device_exists (dev) != TRUE) {			/*Clear error bits in ISR, write 1 to clear */			REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE				   | PCI_ISR_PFE | PCI_ISR_PPE |				   PCI_ISR_AHBE);			continue;		}		/*A device is present, add an entry to the array */		devices[nDevices].bus = bus;		devices[nDevices].device = dev;		devices[nDevices].func = func;		pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16);		devices[nDevices].vendor_id = data16;		pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16);		devices[nDevices].device_id = data16;		/*The device is functioning correctly, set error to FALSE */		devices[nDevices].error = FALSE;		/*Figure out what BARs are on this device */		sys_pci_bar_info_get (nDevices, bus, dev, func);		/*Figure out what INTX# line the card uses */		pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin);		/*assign the appropriate irq line */		if (intPin > PCI_IRQ_LINES) {			devices[nDevices].error = TRUE;		} else if (intPin != 0) {			/*This device uses an interrupt line */			/*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */			devices[nDevices].irq = intPin;		}#ifdef CONFIG_PCI_SCAN_SHOW		printf ("%06d    %03d %03d %04d  %08d      %08x\n", nDevices,			devices[nDevices].vendor_id);#endif		nDevices++;	}	calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE);	sys_pci_device_bars_write ();	REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE		   | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);}void sys_pci_bar_info_get (unsigned int devnum,			   unsigned int bus,			   unsigned int dev, unsigned int func){	unsigned int data32;	unsigned int tmp;	unsigned int size;	pci_write_config_dword (devnum,				PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY);	pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32);	devices[devnum].bar[0].address = (data32 & 1);	if (data32 & 1) {		/* IO space */		tmp = data32 & ~0x3;		size = ~(tmp - 1);		devices[devnum].bar[0].size = size;		if (nIOBars < IXP425_PCI_MAX_BAR) {			ioBars[nIOBars++] = &devices[devnum].bar[0];		}	} else {		/* Mem space */		tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;		size = ~(tmp - 1);		devices[devnum].bar[0].size = size;		if (nMBars < IXP425_PCI_MAX_BAR) {			memBars[nMBars++] = &devices[devnum].bar[0];		} else {			devices[devnum].error = TRUE;		}	}	devices[devnum].bar[1].size = 0;}void sortBars (PciBar * Bars[], unsigned int nBars){	unsigned int i, j;	PciBar *tmp;	if (nBars == 0) {		return;	}	/* Sort biggest to smallest */	for (i = 0; i < nBars - 1; i++) {		for (j = i + 1; j < nBars; j++) {			if (Bars[j]->size > Bars[i]->size) {				/* swap them */				tmp = Bars[i];				Bars[i] = Bars[j];				Bars[j] = tmp;			}		}	}}void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr){	unsigned int i;	if (nBars == 0) {		return;	}	for (i = 0; i < nBars; i++) {		Bars[i]->address |= startAddr;		startAddr += Bars[i]->size;	}}void sys_pci_device_bars_write (void){	unsigned int i;	int addr;	for (i = 1; i < nDevices; i++) {		if (devices[i].error) {			continue;		}		pci_write_config_dword (devices[i].device,					PCI_CFG_BASE_ADDRESS_0,					devices[i].bar[0].address);		addr = BIT (31 - devices[i].device) |			(0 << PCI_NP_AD_FUNCSL) |			(PCI_CFG_BASE_ADDRESS_0 & ~3);		pci_write_config_dword (devices[i].device,					PCI_CFG_DEV_INT_LINE, devices[i].irq);		pci_write_config_word (devices[i].device,				       PCI_CFG_COMMAND, INITIAL_PCI_CMD);	}}int pci_device_exists (unsigned int deviceNo){	unsigned int vendorId;	unsigned int regval;	pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId);	/* There are two ways to find out an empty device.	 *   1. check Master Abort bit after the access.	 *   2. check whether the vendor id read back is 0x0.	 */	REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval);	if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) {		return TRUE;	}	/*no device present, make sure that the master abort bit is reset */	REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE);	return FALSE;}pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo){	unsigned int i;	unsigned int devdidvid;	unsigned int didvid;	unsigned int vendorId, deviceId;	vendorId = ids->vendor;	deviceId = ids->device;	didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) |		(vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK);	for (i = devNo + 1; i < nDevices; i++) {		pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID,				       &devdidvid);		if (devdidvid == didvid) {			return devices[i].device;		}	}	return -1;}#endif	/* CONFIG_PCI */