#include <cdefbf533.h>
#include <defbf533.h>
#define DCPLB_CNT 10
#define ICPLB_CNT 9
#define ENABLE_I_CACHE
#define ENABLE_D_CACHE
#define BOTH_D_CACHE
#pragma align4
section ("data1")
unsigned int D_cplb_addrs[DCPLB_CNT] =
	{
		0xff800000,	
		0xff900000, 
		0x00000000,	
		0x00400000,	
		0x00800000, 
		0x00C00000, 
		0x01000000,	
		0x01400000,	
		0x01800000, 
		0x01C00000 
	};
		
/************************************************/
/*												*/
/*		  Entries for the DCPLBx_DATA			*/
/*												*/
/************************************************/
#pragma align4
section ("data1")
unsigned int D_cplb_data[DCPLB_CNT] =
	{
		0x2001f,
		0x2001f,
		0x3D01f,
		0x3D01f,
		0x3D01f,
		0x3D01f,
		0x3D01f,
		0x3D01f,
		0x3D01f,
		0x3D01f
	};
		
/************************************************/
/*												*/
/*		  Entries for the ICPLBx_ADDR			*/
/*												*/
/************************************************/
#pragma align4
section ("data1")
unsigned int I_cplb_addrs[9] =
	{
		0xFFA00000, 
		0x00000000, 
		0x00400000, 
		0x00800000, 
		0x00C00000, 
		0x01000000, 
		0x01400000, 
		0x01800000, 
		0x01C00000
	};
		
/************************************************/
/*												*/
/*		  Entries for the ICPLBx_DATA			*/
/*												*/
/************************************************/
#pragma align4
section ("data1")
unsigned int I_cplb_data[9] =
	{
		0x00020003,
		0x00031005,
		0x00031005,
		0x00031005,
		0x00031005,
		0x00031005,
		0x00031005,
		0x00031005,
		0x00031005
	};

#pragma align4
section ("data1")
int Lock_Control[4] =
	{
		0,
		0,
		0,
		0
	};
	
void Config_I_Cache(unsigned int *cblb_addr, unsigned int *cplb_data, int cplb_cnt, int no_lru, int *W_Lock)
{
	int temp;
	unsigned int imem_cntrl;
	
	/************************/
	/* CPLBs/Cache disabled */
	/* Invalidate Cache		*/
	/************************/
	*pIMEM_CONTROL = 0x1;
	asm("CSYNC;");
	
	/* Configure the ICPLB_ADDR [n] */
	for (temp=0; temp<cplb_cnt; temp++)
	{
		*(pICPLB_ADDR0 + temp) = *(cblb_addr + temp);
        asm("CSYNC;");
        
	}
	
	/* Configure the ICPLB_DATA [n] */
	for(temp = 0; temp<cplb_cnt; temp++)
    {
    	*(pICPLB_DATA0 + temp) = *(cplb_data + temp);
    	asm("CSYNC;");
    }
	
    /* Enable the ICache and ICPLBs */
    imem_cntrl = 0x7;
    
    /****************************/
    /* Select the LRU Policy 	*/
    /****************************/
    if (no_lru == 1)
    {
    	/* Disable the Modified LRU policy */
    	imem_cntrl |= 0x2000;
    }
    
    /****************************/
    /* Select the Way Locking 	*/
    /****************************/
    if (*W_Lock == 1)
    {
    	/* Lock Way 0 */
    	imem_cntrl |= 0x8;
    }
    if (*(W_Lock+1) == 1)
    {
    	/* Lock Way 1 */
    	imem_cntrl |= 0x10;
    }
    if (*(W_Lock+2) == 1)
    {
    	/* Lock Way 1 */
    	imem_cntrl |= 0x20;
    }
    if (*(W_Lock+3) == 1)
    {
    	/* Lock Way 1 */
    	imem_cntrl |= 0x40;
    }
    
	/* Enable the Instruction Cache and CPLBs */
	*pIMEM_CONTROL = imem_cntrl;
	asm("SSYNC;");
	
} /* Config_I_Cache */

void Config_D_Cache(unsigned int *cplb_addr, unsigned int *cplb_data, int cplb_cnt, int banks)
{		
		int temp;
		
		/************************/
		/* Disable the DCPLBs	*/
		/* Disable the D_Cache	*/
		/* Invalidate Cache 	*/
		/************************/
		*pDMEM_CONTROL = 0x1;
		asm("CSYNC;");
        
		/* Configure the CPLB_ADDR Entries	*/
        for(temp = 0; temp<cplb_cnt; temp++)
        {
        	*(pDCPLB_ADDR0 + temp) = *(cplb_addr + temp);
        	asm("CSYNC;");
        }
		
        /* Configure DCPLB_DATA entries */
        for(temp = 0; temp<cplb_cnt; temp++)
        {
        	*(pDCPLB_DATA0 + temp) = *(cplb_data + temp);
        	asm("CSYNC;");
        }
		
        /* Enable Cache, Enable CPLBs */
        if (banks == 1)
        {
       		/* Only one bank-A enabled as Cache */
       		*pDMEM_CONTROL = 0x100B;
       		asm("ssync;");
        }
        else
        {
        	if (banks == 2)
        	{
        		/* Both the banks enabled as Cache */
        		*pDMEM_CONTROL = 0x100F;
        		asm("ssync;");
        	}
        }
        
} /*Config_D_Cache */

void cacheinit()
{
	int i;
	int dcplb_cnt, icplb_cnt, d_bank_cnt, disable_lru;

	/****************************************************/
	/* Configure the DCPLBs and Enabled the Data Cache 	*/
	/****************************************************/
#ifdef ENABLE_D_CACHE
	dcplb_cnt = DCPLB_CNT;
	#ifdef BOTH_D_CACHE
		d_bank_cnt = 2;
	#else
		d_bank_cnt = 1; 
	#endif
	Config_D_Cache(D_cplb_addrs, D_cplb_data, dcplb_cnt, d_bank_cnt);
#endif	


	/****************************************************/
	/* Configure the DCPLBs and Enabled the Data Cache 	*/
	/* Enabled all ways 								*/
	/* Use Modified LRU policy 							*/
	/****************************************************/
#ifdef ENABLE_I_CACHE
	icplb_cnt = ICPLB_CNT;
	disable_lru = 0;
	Config_I_Cache(I_cplb_addrs, I_cplb_data, icplb_cnt, disable_lru, Lock_Control);
#endif	
}